From 888df264aa7c71281d5c95b521a91a3639bc3ab2 Mon Sep 17 00:00:00 2001 From: Martin Stransky Date: Mon, 30 May 2022 21:40:33 +0200 Subject: Update to 101.0 --- .gitignore | 2 + D142373.diff | 86 - D145094.diff | 61 - D145541.diff | 21 - firefox.spec | 19 +- libwebrtc-screen-cast-sync.patch | 4765 ++++++++++++++++++-------------------- mozilla-1663844.patch | 33 +- sources | 4 +- 8 files changed, 2294 insertions(+), 2697 deletions(-) delete mode 100644 D142373.diff delete mode 100644 D145094.diff delete mode 100644 D145541.diff diff --git a/.gitignore b/.gitignore index 9dbb896..9cb84f4 100644 --- a/.gitignore +++ b/.gitignore @@ -511,3 +511,5 @@ firefox-3.6.4.source.tar.bz2 /firefox-langpacks-100.0.1-20220518.tar.xz /firefox-100.0.2.source.tar.xz /firefox-langpacks-100.0.2-20220520.tar.xz +/firefox-101.0.source.tar.xz +/firefox-langpacks-101.0-20220530.tar.xz diff --git a/D142373.diff b/D142373.diff deleted file mode 100644 index 932cf7a..0000000 --- a/D142373.diff +++ /dev/null @@ -1,86 +0,0 @@ -diff --git a/python/mozbuild/mozbuild/build_commands.py b/python/mozbuild/mozbuild/build_commands.py ---- a/python/mozbuild/mozbuild/build_commands.py -+++ b/python/mozbuild/mozbuild/build_commands.py -@@ -183,10 +183,11 @@ - directory=directory, - verbose=verbose, - keep_going=keep_going, - mach_context=command_context._mach_context, - append_env=append_env, -+ virtualenv_topobjdir=orig_topobjdir, - ) - if status != 0: - return status - - # Packaging the instrumented build is required to get the jarlog -@@ -206,11 +207,11 @@ - pgo_env["LLVM_PROFDATA"] = instr.config_environment.substs.get( - "LLVM_PROFDATA" - ) - pgo_env["JARLOG_FILE"] = mozpath.join(orig_topobjdir, "jarlog/en-US.log") - pgo_cmd = [ -- instr.virtualenv_manager.python_path, -+ command_context.virtualenv_manager.python_path, - mozpath.join(command_context.topsrcdir, "build/pgo/profileserver.py"), - ] - subprocess.check_call(pgo_cmd, cwd=instr.topobjdir, env=pgo_env) - - # Set the default build to MOZ_PROFILE_USE -diff --git a/python/mozbuild/mozbuild/controller/building.py b/python/mozbuild/mozbuild/controller/building.py ---- a/python/mozbuild/mozbuild/controller/building.py -+++ b/python/mozbuild/mozbuild/controller/building.py -@@ -1220,10 +1220,11 @@ - directory=None, - verbose=False, - keep_going=False, - mach_context=None, - append_env=None, -+ virtualenv_topobjdir=None, - ): - """Invoke the build backend. - - ``what`` defines the thing to build. If not defined, the default - target is used. -@@ -1297,10 +1298,11 @@ - config_rc = self.configure( - metrics, - buildstatus_messages=True, - line_handler=output.on_line, - append_env=append_env, -+ virtualenv_topobjdir=virtualenv_topobjdir, - ) - - if config_rc != 0: - return config_rc - -@@ -1635,10 +1637,11 @@ - metrics, - options=None, - buildstatus_messages=False, - line_handler=None, - append_env=None, -+ virtualenv_topobjdir=None, - ): - # Disable indexing in objdir because it is not necessary and can slow - # down builds. - self.metrics = metrics - mkdir(self.topobjdir, not_indexed=True) -@@ -1658,15 +1661,16 @@ - if line.startswith("export "): - k, eq, v = line[len("export ") :].partition("=") - if eq == "=": - append_env[k] = v - -+ virtualenv_topobjdir = virtualenv_topobjdir or self.topobjdir - build_site = CommandSiteManager.from_environment( - self.topsrcdir, - lambda: get_state_dir(specific_to_topsrcdir=True, topsrcdir=self.topsrcdir), - "build", -- os.path.join(self.topobjdir, "_virtualenvs"), -+ os.path.join(virtualenv_topobjdir, "_virtualenvs"), - ) - build_site.ensure() - - command = [build_site.python_path, os.path.join(self.topsrcdir, "configure.py")] - if options: - diff --git a/D145094.diff b/D145094.diff deleted file mode 100644 index 711acc9..0000000 --- a/D145094.diff +++ /dev/null @@ -1,61 +0,0 @@ -diff -up firefox-100.0/dom/media/platforms/ffmpeg/FFmpegVideoFramePool.cpp.D145094 firefox-100.0/dom/media/platforms/ffmpeg/FFmpegVideoFramePool.cpp ---- firefox-100.0/dom/media/platforms/ffmpeg/FFmpegVideoFramePool.cpp.D145094 2022-04-29 01:01:46.000000000 +0200 -+++ firefox-100.0/dom/media/platforms/ffmpeg/FFmpegVideoFramePool.cpp 2022-05-03 09:51:48.570471687 +0200 -@@ -23,7 +23,7 @@ RefPtr VideoFrameSurface< - VideoFrameSurface::VideoFrameSurface(DMABufSurface* aSurface) - : mSurface(aSurface), - mLib(nullptr), -- mAVHWDeviceContext(nullptr), -+ mAVHWFrameContext(nullptr), - mHWAVBuffer(nullptr) { - // Create global refcount object to track mSurface usage over - // gects rendering engine. We can't release it until it's used -@@ -38,16 +38,22 @@ VideoFrameSurface::VideoFrame - void VideoFrameSurface::LockVAAPIData( - AVCodecContext* aAVCodecContext, AVFrame* aAVFrame, - FFmpegLibWrapper* aLib) { -- FFMPEG_LOG("VideoFrameSurface: VAAPI locking dmabuf surface UID = %d", -- mSurface->GetUID()); -+ MOZ_DIAGNOSTIC_ASSERT(aAVCodecContext->hw_frames_ctx); - mLib = aLib; -- mAVHWDeviceContext = aLib->av_buffer_ref(aAVCodecContext->hw_device_ctx); -+ mAVHWFrameContext = aLib->av_buffer_ref(aAVCodecContext->hw_frames_ctx); - mHWAVBuffer = aLib->av_buffer_ref(aAVFrame->buf[0]); -+ FFMPEG_LOG( -+ "VideoFrameSurface: VAAPI locking dmabuf surface UID = %d " -+ "mAVHWFrameContext %p mHWAVBuffer %p", -+ mSurface->GetUID(), mAVHWFrameContext, mHWAVBuffer); - } - - void VideoFrameSurface::ReleaseVAAPIData(bool aForFrameRecycle) { -- FFMPEG_LOG("VideoFrameSurface: VAAPI releasing dmabuf surface UID = %d", -- mSurface->GetUID()); -+ FFMPEG_LOG( -+ "VideoFrameSurface: VAAPI releasing dmabuf surface UID = %d " -+ "aForFrameRecycle %d mLib %p mAVHWFrameContext %p mHWAVBuffer %p", -+ mSurface->GetUID(), aForFrameRecycle, mLib, mAVHWFrameContext, -+ mHWAVBuffer); - - // It's possible to unref GPU data while IsUsed() is still set. - // It can happens when VideoFramePool is deleted while decoder shutdown -@@ -57,7 +63,7 @@ void VideoFrameSurface::Relea - // is closed. - if (mLib) { - mLib->av_buffer_unref(&mHWAVBuffer); -- mLib->av_buffer_unref(&mAVHWDeviceContext); -+ mLib->av_buffer_unref(&mAVHWFrameContext); - } - - // If we want to recycle the frame, make sure it's not used -diff -up firefox-100.0/dom/media/platforms/ffmpeg/FFmpegVideoFramePool.h.D145094 firefox-100.0/dom/media/platforms/ffmpeg/FFmpegVideoFramePool.h ---- firefox-100.0/dom/media/platforms/ffmpeg/FFmpegVideoFramePool.h.D145094 2022-04-29 00:02:40.000000000 +0200 -+++ firefox-100.0/dom/media/platforms/ffmpeg/FFmpegVideoFramePool.h 2022-05-03 09:33:27.110885715 +0200 -@@ -102,7 +102,7 @@ class VideoFrameSurface { - - const RefPtr mSurface; - const FFmpegLibWrapper* mLib; -- AVBufferRef* mAVHWDeviceContext; -+ AVBufferRef* mAVHWFrameContext; - AVBufferRef* mHWAVBuffer; - }; - diff --git a/D145541.diff b/D145541.diff deleted file mode 100644 index 7ca3a2e..0000000 --- a/D145541.diff +++ /dev/null @@ -1,21 +0,0 @@ -diff --git a/widget/gtk/MozContainerWayland.cpp b/widget/gtk/MozContainerWayland.cpp ---- a/widget/gtk/MozContainerWayland.cpp -+++ b/widget/gtk/MozContainerWayland.cpp -@@ -527,10 +527,16 @@ - return; - } - - LOGWAYLAND("%s [%p] scale %d\n", __FUNCTION__, - (void*)moz_container_get_nsWindow(container), scale); -+ // There is a chance that the attached wl_buffer has not yet been doubled -+ // on the main thread when scale factor changed to 2. This leads to -+ // crash with the following message: -+ // Buffer size (AxB) must be an integer multiple of the buffer_scale (2) -+ // Removing the possibly wrong wl_buffer to prevent that crash: -+ wl_surface_attach(wl_container->surface, nullptr, 0, 0); - wl_surface_set_buffer_scale(wl_container->surface, scale); - wl_container->buffer_scale = scale; - } - } - - diff --git a/firefox.spec b/firefox.spec index 40f6e66..3206448 100644 --- a/firefox.spec +++ b/firefox.spec @@ -124,9 +124,9 @@ ExcludeArch: aarch64 %endif %if %{?system_nss} -%global nspr_version 4.26 +%global nspr_version 4.32 %global nspr_build_version %{nspr_version} -%global nss_version 3.76 +%global nss_version 3.78 %global nss_build_version %{nss_version} %endif @@ -162,13 +162,13 @@ ExcludeArch: aarch64 Summary: Mozilla Firefox Web browser Name: firefox -Version: 100.0.2 -Release: 2%{?pre_tag}%{?dist} +Version: 101.0 +Release: 1%{?pre_tag}%{?dist} URL: https://www.mozilla.org/firefox/ License: MPLv1.1 or GPLv2+ or LGPLv2+ Source0: https://archive.mozilla.org/pub/firefox/releases/%{version}%{?pre_version}/source/firefox-%{version}%{?pre_version}.source.tar.xz %if %{with langpacks} -Source1: firefox-langpacks-%{version}%{?pre_version}-20220520.tar.xz +Source1: firefox-langpacks-%{version}%{?pre_version}-20220530.tar.xz %endif Source2: cbindgen-vendor.tar.xz Source10: firefox-mozconfig @@ -217,7 +217,6 @@ Patch55: firefox-testing.patch Patch61: firefox-glibc-dynstack.patch Patch62: build-python.patch Patch71: 0001-GLIBCXX-fix-for-GCC-12.patch -Patch72: D142373.diff Patch73: D147266.diff Patch74: D147267.diff @@ -243,8 +242,6 @@ Patch402: mozilla-1196777.patch Patch407: mozilla-1667096.patch Patch408: mozilla-1663844.patch Patch415: mozilla-1670333.patch -Patch416: D145094.diff -Patch417: D145541.diff Patch418: mozilla-1767946-profilemanagersize.patch # PGO/LTO patches @@ -463,7 +460,6 @@ This package contains results of tests executed during build. %patch53 -p1 -b .firefox-gcc-build %patch54 -p1 -b .1669639 %patch71 -p1 -b .0001-GLIBCXX-fix-for-GCC-12 -%patch72 -p1 -b .D142373 %patch73 -p1 -b .D147266 %patch74 -p1 -b .D147267 @@ -487,8 +483,6 @@ This package contains results of tests executed during build. %patch407 -p1 -b .1667096 %patch408 -p1 -b .1663844 %patch415 -p1 -b .1670333 -%patch416 -p1 -b .D145094 -%patch417 -p1 -b .D145541 %patch418 -p1 -b .mozilla-1767946-profilemanagersize # PGO patches @@ -1063,6 +1057,9 @@ gtk-update-icon-cache %{_datadir}/icons/hicolor &>/dev/null || : #--------------------------------------------------------------------- %changelog +* Mon May 30 2022 Martin Stransky - 101.0-1 +- Updated to 101.0 + * Wed May 25 2022 Martin Stransky - 100.0.2-2 - Added fix for mzbz#1771104 diff --git a/libwebrtc-screen-cast-sync.patch b/libwebrtc-screen-cast-sync.patch index 09bfd0f..fab5b5c 100644 --- a/libwebrtc-screen-cast-sync.patch +++ b/libwebrtc-screen-cast-sync.patch @@ -1,13 +1,6 @@ -From e0e925da71abb97a60d02716b18faa19a29fada6 Mon Sep 17 00:00:00 2001 -From: Jan Grulich -Date: Mon, 21 Feb 2022 15:34:52 +0100 -Subject: WebRTC - screen cast sync - - -diff --git a/dom/media/webrtc/third_party_build/moz.build b/dom/media/webrtc/third_party_build/moz.build -index e4c7ba7..a42f913 100644 ---- a/dom/media/webrtc/third_party_build/moz.build -+++ b/dom/media/webrtc/third_party_build/moz.build +diff -up firefox-101.0/dom/media/webrtc/third_party_build/moz.build.libwebrtc-screen-cast-sync firefox-101.0/dom/media/webrtc/third_party_build/moz.build +--- firefox-101.0/dom/media/webrtc/third_party_build/moz.build.libwebrtc-screen-cast-sync 2022-05-27 01:16:54.000000000 +0200 ++++ firefox-101.0/dom/media/webrtc/third_party_build/moz.build 2022-05-30 21:33:19.740522043 +0200 @@ -63,6 +63,8 @@ webrtc_non_unified_sources = [ if CONFIG["MOZ_WIDGET_TOOLKIT"] == "gtk": @@ -17,35 +10,12 @@ index e4c7ba7..a42f913 100644 GN_DIRS += ["../../../../third_party/libwebrtc"] -diff --git a/third_party/drm/README b/third_party/drm/README -new file mode 100644 -index 0000000..f68ed10 ---- /dev/null -+++ b/third_party/drm/README -@@ -0,0 +1,4 @@ -+Libdrm is a drm library wrapper needed to build and run Firefox with -+Pipewire support on Linux (https://gitlab.freedesktop.org/mesa/drm). -+ -+libdrm directory stores headers of libdrm needed for build only. -diff --git a/third_party/drm/drm/drm.h b/third_party/drm/drm/drm.h -new file mode 100644 -index 0000000..5e54c3a ---- /dev/null -+++ b/third_party/drm/drm/drm.h -@@ -0,0 +1,1193 @@ -+/* -+ * Header for the Direct Rendering Manager -+ * -+ * Author: Rickard E. (Rik) Faith -+ * -+ * Acknowledgments: -+ * Dec 1999, Richard Henderson , move to generic cmpxchg. -+ */ -+ +diff -up firefox-101.0/third_party/drm/drm/drm_fourcc.h.libwebrtc-screen-cast-sync firefox-101.0/third_party/drm/drm/drm_fourcc.h +--- firefox-101.0/third_party/drm/drm/drm_fourcc.h.libwebrtc-screen-cast-sync 2022-05-30 21:33:19.741522076 +0200 ++++ firefox-101.0/third_party/drm/drm/drm_fourcc.h 2022-05-30 21:33:19.741522076 +0200 +@@ -0,0 +1,1377 @@ +/* -+ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. -+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. -+ * All rights reserved. ++ * Copyright 2011 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), @@ -67,1173 +37,1377 @@ index 0000000..5e54c3a + * OTHER DEALINGS IN THE SOFTWARE. + */ + -+#ifndef _DRM_H_ -+#define _DRM_H_ -+ -+#if defined(__linux__) -+ -+#include -+#include -+typedef unsigned int drm_handle_t; -+ -+#else /* One of the BSDs */ -+ -+#include -+#include -+#include -+typedef int8_t __s8; -+typedef uint8_t __u8; -+typedef int16_t __s16; -+typedef uint16_t __u16; -+typedef int32_t __s32; -+typedef uint32_t __u32; -+typedef int64_t __s64; -+typedef uint64_t __u64; -+typedef size_t __kernel_size_t; -+typedef unsigned long drm_handle_t; ++#ifndef DRM_FOURCC_H ++#define DRM_FOURCC_H + -+#endif ++#include "drm.h" + +#if defined(__cplusplus) +extern "C" { +#endif + -+#define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */ -+#define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */ -+#define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */ -+#define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */ -+ -+#define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */ -+#define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */ -+#define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD) -+#define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT) -+#define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT)) -+ -+typedef unsigned int drm_context_t; -+typedef unsigned int drm_drawable_t; -+typedef unsigned int drm_magic_t; -+ -+/* -+ * Cliprect. ++/** ++ * DOC: overview + * -+ * \warning: If you change this structure, make sure you change -+ * XF86DRIClipRectRec in the server as well ++ * In the DRM subsystem, framebuffer pixel formats are described using the ++ * fourcc codes defined in `include/uapi/drm/drm_fourcc.h`. In addition to the ++ * fourcc code, a Format Modifier may optionally be provided, in order to ++ * further describe the buffer's format - for example tiling or compression. + * -+ * \note KW: Actually it's illegal to change either for -+ * backwards-compatibility reasons. -+ */ -+struct drm_clip_rect { -+ unsigned short x1; -+ unsigned short y1; -+ unsigned short x2; -+ unsigned short y2; -+}; -+ -+/* -+ * Drawable information. ++ * Format Modifiers ++ * ---------------- ++ * ++ * Format modifiers are used in conjunction with a fourcc code, forming a ++ * unique fourcc:modifier pair. This format:modifier pair must fully define the ++ * format and data layout of the buffer, and should be the only way to describe ++ * that particular buffer. ++ * ++ * Having multiple fourcc:modifier pairs which describe the same layout should ++ * be avoided, as such aliases run the risk of different drivers exposing ++ * different names for the same data format, forcing userspace to understand ++ * that they are aliases. ++ * ++ * Format modifiers may change any property of the buffer, including the number ++ * of planes and/or the required allocation size. Format modifiers are ++ * vendor-namespaced, and as such the relationship between a fourcc code and a ++ * modifier is specific to the modifer being used. For example, some modifiers ++ * may preserve meaning - such as number of planes - from the fourcc code, ++ * whereas others may not. ++ * ++ * Modifiers must uniquely encode buffer layout. In other words, a buffer must ++ * match only a single modifier. A modifier must not be a subset of layouts of ++ * another modifier. For instance, it's incorrect to encode pitch alignment in ++ * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel ++ * aligned modifier. That said, modifiers can have implicit minimal ++ * requirements. ++ * ++ * For modifiers where the combination of fourcc code and modifier can alias, ++ * a canonical pair needs to be defined and used by all drivers. Preferred ++ * combinations are also encouraged where all combinations might lead to ++ * confusion and unnecessarily reduced interoperability. An example for the ++ * latter is AFBC, where the ABGR layouts are preferred over ARGB layouts. ++ * ++ * There are two kinds of modifier users: ++ * ++ * - Kernel and user-space drivers: for drivers it's important that modifiers ++ * don't alias, otherwise two drivers might support the same format but use ++ * different aliases, preventing them from sharing buffers in an efficient ++ * format. ++ * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users ++ * see modifiers as opaque tokens they can check for equality and intersect. ++ * These users musn't need to know to reason about the modifier value ++ * (i.e. they are not expected to extract information out of the modifier). ++ * ++ * Vendors should document their modifier usage in as much detail as ++ * possible, to ensure maximum compatibility across devices, drivers and ++ * applications. ++ * ++ * The authoritative list of format modifier codes is found in ++ * `include/uapi/drm/drm_fourcc.h` + */ -+struct drm_drawable_info { -+ unsigned int num_rects; -+ struct drm_clip_rect *rects; -+}; + -+/* -+ * Texture region, -+ */ -+struct drm_tex_region { -+ unsigned char next; -+ unsigned char prev; -+ unsigned char in_use; -+ unsigned char padding; -+ unsigned int age; -+}; ++#define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \ ++ ((__u32)(c) << 16) | ((__u32)(d) << 24)) + -+/* -+ * Hardware lock. -+ * -+ * The lock structure is a simple cache-line aligned integer. To avoid -+ * processor bus contention on a multiprocessor system, there should not be any -+ * other data stored in the same cache line. -+ */ -+struct drm_hw_lock { -+ __volatile__ unsigned int lock; /**< lock variable */ -+ char padding[60]; /**< Pad to cache line */ -+}; ++#define DRM_FORMAT_BIG_ENDIAN (1U<<31) /* format is big endian instead of little endian */ + -+/* -+ * DRM_IOCTL_VERSION ioctl argument type. -+ * -+ * \sa drmGetVersion(). -+ */ -+struct drm_version { -+ int version_major; /**< Major version */ -+ int version_minor; /**< Minor version */ -+ int version_patchlevel; /**< Patch level */ -+ __kernel_size_t name_len; /**< Length of name buffer */ -+ char *name; /**< Name of driver */ -+ __kernel_size_t date_len; /**< Length of date buffer */ -+ char *date; /**< User-space buffer to hold date */ -+ __kernel_size_t desc_len; /**< Length of desc buffer */ -+ char *desc; /**< User-space buffer to hold desc */ -+}; ++/* Reserve 0 for the invalid format specifier */ ++#define DRM_FORMAT_INVALID 0 + -+/* -+ * DRM_IOCTL_GET_UNIQUE ioctl argument type. -+ * -+ * \sa drmGetBusid() and drmSetBusId(). -+ */ -+struct drm_unique { -+ __kernel_size_t unique_len; /**< Length of unique */ -+ char *unique; /**< Unique name for driver instantiation */ -+}; ++/* color index */ ++#define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */ + -+struct drm_list { -+ int count; /**< Length of user-space structures */ -+ struct drm_version *version; -+}; ++/* 8 bpp Red */ ++#define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */ + -+struct drm_block { -+ int unused; -+}; ++/* 10 bpp Red */ ++#define DRM_FORMAT_R10 fourcc_code('R', '1', '0', ' ') /* [15:0] x:R 6:10 little endian */ + -+/* -+ * DRM_IOCTL_CONTROL ioctl argument type. -+ * -+ * \sa drmCtlInstHandler() and drmCtlUninstHandler(). -+ */ -+struct drm_control { -+ enum { -+ DRM_ADD_COMMAND, -+ DRM_RM_COMMAND, -+ DRM_INST_HANDLER, -+ DRM_UNINST_HANDLER -+ } func; -+ int irq; -+}; ++/* 12 bpp Red */ ++#define DRM_FORMAT_R12 fourcc_code('R', '1', '2', ' ') /* [15:0] x:R 4:12 little endian */ + -+/* -+ * Type of memory to map. -+ */ -+enum drm_map_type { -+ _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */ -+ _DRM_REGISTERS = 1, /**< no caching, no core dump */ -+ _DRM_SHM = 2, /**< shared, cached */ -+ _DRM_AGP = 3, /**< AGP/GART */ -+ _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */ -+ _DRM_CONSISTENT = 5 /**< Consistent memory for PCI DMA */ -+}; ++/* 16 bpp Red */ ++#define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */ + -+/* -+ * Memory mapping flags. -+ */ -+enum drm_map_flags { -+ _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */ -+ _DRM_READ_ONLY = 0x02, -+ _DRM_LOCKED = 0x04, /**< shared, cached, locked */ -+ _DRM_KERNEL = 0x08, /**< kernel requires access */ -+ _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */ -+ _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */ -+ _DRM_REMOVABLE = 0x40, /**< Removable mapping */ -+ _DRM_DRIVER = 0x80 /**< Managed by driver */ -+}; ++/* 16 bpp RG */ ++#define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */ ++#define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */ + -+struct drm_ctx_priv_map { -+ unsigned int ctx_id; /**< Context requesting private mapping */ -+ void *handle; /**< Handle of map */ -+}; ++/* 32 bpp RG */ ++#define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */ ++#define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */ + -+/* -+ * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls -+ * argument type. -+ * -+ * \sa drmAddMap(). -+ */ -+struct drm_map { -+ unsigned long offset; /**< Requested physical address (0 for SAREA)*/ -+ unsigned long size; /**< Requested physical size (bytes) */ -+ enum drm_map_type type; /**< Type of memory to map */ -+ enum drm_map_flags flags; /**< Flags */ -+ void *handle; /**< User-space: "Handle" to pass to mmap() */ -+ /**< Kernel-space: kernel-virtual address */ -+ int mtrr; /**< MTRR slot used */ -+ /* Private data */ -+}; ++/* 8 bpp RGB */ ++#define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */ ++#define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */ + -+/* -+ * DRM_IOCTL_GET_CLIENT ioctl argument type. -+ */ -+struct drm_client { -+ int idx; /**< Which client desired? */ -+ int auth; /**< Is client authenticated? */ -+ unsigned long pid; /**< Process ID */ -+ unsigned long uid; /**< User ID */ -+ unsigned long magic; /**< Magic */ -+ unsigned long iocs; /**< Ioctl count */ -+}; ++/* 16 bpp RGB */ ++#define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */ ++#define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */ ++#define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */ ++#define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */ + -+enum drm_stat_type { -+ _DRM_STAT_LOCK, -+ _DRM_STAT_OPENS, -+ _DRM_STAT_CLOSES, -+ _DRM_STAT_IOCTLS, -+ _DRM_STAT_LOCKS, -+ _DRM_STAT_UNLOCKS, -+ _DRM_STAT_VALUE, /**< Generic value */ -+ _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */ -+ _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */ ++#define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */ ++#define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */ ++#define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */ ++#define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */ + -+ _DRM_STAT_IRQ, /**< IRQ */ -+ _DRM_STAT_PRIMARY, /**< Primary DMA bytes */ -+ _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */ -+ _DRM_STAT_DMA, /**< DMA */ -+ _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */ -+ _DRM_STAT_MISSED /**< Missed DMA opportunity */ -+ /* Add to the *END* of the list */ -+}; ++#define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */ ++#define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */ ++#define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */ ++#define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */ ++ ++#define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */ ++#define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */ ++#define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */ ++#define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */ ++ ++#define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */ ++#define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */ ++ ++/* 24 bpp RGB */ ++#define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */ ++#define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */ ++ ++/* 32 bpp RGB */ ++#define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */ ++#define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */ ++#define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */ ++#define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */ ++ ++#define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */ ++#define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */ ++#define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */ ++#define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */ ++ ++#define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */ ++#define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */ ++#define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */ ++#define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */ ++ ++#define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */ ++#define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */ ++#define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */ ++#define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */ ++ ++/* 64 bpp RGB */ ++#define DRM_FORMAT_XRGB16161616 fourcc_code('X', 'R', '4', '8') /* [63:0] x:R:G:B 16:16:16:16 little endian */ ++#define DRM_FORMAT_XBGR16161616 fourcc_code('X', 'B', '4', '8') /* [63:0] x:B:G:R 16:16:16:16 little endian */ ++ ++#define DRM_FORMAT_ARGB16161616 fourcc_code('A', 'R', '4', '8') /* [63:0] A:R:G:B 16:16:16:16 little endian */ ++#define DRM_FORMAT_ABGR16161616 fourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 little endian */ + +/* -+ * DRM_IOCTL_GET_STATS ioctl argument type. ++ * Floating point 64bpp RGB ++ * IEEE 754-2008 binary16 half-precision float ++ * [15:0] sign:exponent:mantissa 1:5:10 + */ -+struct drm_stats { -+ unsigned long count; -+ struct { -+ unsigned long value; -+ enum drm_stat_type type; -+ } data[15]; -+}; ++#define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */ ++#define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */ ++ ++#define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */ ++#define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */ + +/* -+ * Hardware locking flags. ++ * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits ++ * of unused padding per component: + */ -+enum drm_lock_flags { -+ _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */ -+ _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */ -+ _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */ -+ _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */ -+ /* These *HALT* flags aren't supported yet -+ -- they will be used to support the -+ full-screen DGA-like mode. */ -+ _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */ -+ _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */ -+}; ++#define DRM_FORMAT_AXBXGXRX106106106106 fourcc_code('A', 'B', '1', '0') /* [63:0] A:x:B:x:G:x:R:x 10:6:10:6:10:6:10:6 little endian */ ++ ++/* packed YCbCr */ ++#define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */ ++#define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */ ++#define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */ ++#define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */ ++ ++#define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */ ++#define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */ ++#define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */ ++#define DRM_FORMAT_VUY101010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */ + +/* -+ * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type. -+ * -+ * \sa drmGetLock() and drmUnlock(). ++ * packed Y2xx indicate for each component, xx valid data occupy msb ++ * 16-xx padding occupy lsb + */ -+struct drm_lock { -+ int context; -+ enum drm_lock_flags flags; -+}; ++#define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 10:6:10:6:10:6:10:6 little endian per 2 Y pixels */ ++#define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 12:4:12:4:12:4:12:4 little endian per 2 Y pixels */ ++#define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0] Cr0:Y1:Cb0:Y0 16:16:16:16 little endian per 2 Y pixels */ + +/* -+ * DMA flags -+ * -+ * \warning -+ * These values \e must match xf86drm.h. -+ * -+ * \sa drm_dma. ++ * packed Y4xx indicate for each component, xx valid data occupy msb ++ * 16-xx padding occupy lsb except Y410 + */ -+enum drm_dma_flags { -+ /* Flags for DMA buffer dispatch */ -+ _DRM_DMA_BLOCK = 0x01, /**< -+ * Block until buffer dispatched. -+ * -+ * \note The buffer may not yet have -+ * been processed by the hardware -- -+ * getting a hardware lock with the -+ * hardware quiescent will ensure -+ * that the buffer has been -+ * processed. -+ */ -+ _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */ -+ _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */ ++#define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 little endian */ ++#define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */ ++#define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 little endian */ + -+ /* Flags for DMA buffer request */ -+ _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */ -+ _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */ -+ _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */ -+}; ++#define DRM_FORMAT_XVYU2101010 fourcc_code('X', 'V', '3', '0') /* [31:0] X:Cr:Y:Cb 2:10:10:10 little endian */ ++#define DRM_FORMAT_XVYU12_16161616 fourcc_code('X', 'V', '3', '6') /* [63:0] X:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */ ++#define DRM_FORMAT_XVYU16161616 fourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 little endian */ + +/* -+ * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type. -+ * -+ * \sa drmAddBufs(). ++ * packed YCbCr420 2x2 tiled formats ++ * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile + */ -+struct drm_buf_desc { -+ int count; /**< Number of buffers of this size */ -+ int size; /**< Size in bytes */ -+ int low_mark; /**< Low water mark */ -+ int high_mark; /**< High water mark */ -+ enum { -+ _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */ -+ _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */ -+ _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */ -+ _DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */ -+ _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */ -+ } flags; -+ unsigned long agp_start; /**< -+ * Start address of where the AGP buffers are -+ * in the AGP aperture -+ */ -+}; ++/* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */ ++#define DRM_FORMAT_Y0L0 fourcc_code('Y', '0', 'L', '0') ++/* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */ ++#define DRM_FORMAT_X0L0 fourcc_code('X', '0', 'L', '0') + -+/* -+ * DRM_IOCTL_INFO_BUFS ioctl argument type. -+ */ -+struct drm_buf_info { -+ int count; /**< Entries in list */ -+ struct drm_buf_desc *list; -+}; ++/* [63:0] A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */ ++#define DRM_FORMAT_Y0L2 fourcc_code('Y', '0', 'L', '2') ++/* [63:0] X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */ ++#define DRM_FORMAT_X0L2 fourcc_code('X', '0', 'L', '2') + +/* -+ * DRM_IOCTL_FREE_BUFS ioctl argument type. ++ * 1-plane YUV 4:2:0 ++ * In these formats, the component ordering is specified (Y, followed by U ++ * then V), but the exact Linear layout is undefined. ++ * These formats can only be used with a non-Linear modifier. + */ -+struct drm_buf_free { -+ int count; -+ int *list; -+}; ++#define DRM_FORMAT_YUV420_8BIT fourcc_code('Y', 'U', '0', '8') ++#define DRM_FORMAT_YUV420_10BIT fourcc_code('Y', 'U', '1', '0') + +/* -+ * Buffer information -+ * -+ * \sa drm_buf_map. ++ * 2 plane RGB + A ++ * index 0 = RGB plane, same format as the corresponding non _A8 format has ++ * index 1 = A plane, [7:0] A + */ -+struct drm_buf_pub { -+ int idx; /**< Index into the master buffer list */ -+ int total; /**< Buffer size */ -+ int used; /**< Amount of buffer in use (for DMA) */ -+ void *address; /**< Address of buffer */ -+}; ++#define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8') ++#define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8') ++#define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8') ++#define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8') ++#define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8') ++#define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8') ++#define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8') ++#define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8') + +/* -+ * DRM_IOCTL_MAP_BUFS ioctl argument type. ++ * 2 plane YCbCr ++ * index 0 = Y plane, [7:0] Y ++ * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian ++ * or ++ * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian + */ -+struct drm_buf_map { -+ int count; /**< Length of the buffer list */ -+#ifdef __cplusplus -+ void *virt; -+#else -+ void *virtual; /**< Mmap'd area in user-virtual */ -+#endif -+ struct drm_buf_pub *list; /**< Buffer information */ -+}; -+ ++#define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */ ++#define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */ ++#define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */ ++#define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */ ++#define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */ ++#define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */ +/* -+ * DRM_IOCTL_DMA ioctl argument type. -+ * -+ * Indices here refer to the offset into the buffer list in drm_buf_get. -+ * -+ * \sa drmDMA(). ++ * 2 plane YCbCr ++ * index 0 = Y plane, [39:0] Y3:Y2:Y1:Y0 little endian ++ * index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian + */ -+struct drm_dma { -+ int context; /**< Context handle */ -+ int send_count; /**< Number of buffers to send */ -+ int *send_indices; /**< List of handles to buffers */ -+ int *send_sizes; /**< Lengths of data to send */ -+ enum drm_dma_flags flags; /**< Flags */ -+ int request_count; /**< Number of buffers requested */ -+ int request_size; /**< Desired size for buffers */ -+ int *request_indices; /**< Buffer information */ -+ int *request_sizes; -+ int granted_count; /**< Number of buffers granted */ -+}; -+ -+enum drm_ctx_flags { -+ _DRM_CONTEXT_PRESERVED = 0x01, -+ _DRM_CONTEXT_2DONLY = 0x02 -+}; ++#define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */ + +/* -+ * DRM_IOCTL_ADD_CTX ioctl argument type. -+ * -+ * \sa drmCreateContext() and drmDestroyContext(). ++ * 2 plane YCbCr MSB aligned ++ * index 0 = Y plane, [15:0] Y:x [10:6] little endian ++ * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian + */ -+struct drm_ctx { -+ drm_context_t handle; -+ enum drm_ctx_flags flags; -+}; ++#define DRM_FORMAT_P210 fourcc_code('P', '2', '1', '0') /* 2x1 subsampled Cr:Cb plane, 10 bit per channel */ + +/* -+ * DRM_IOCTL_RES_CTX ioctl argument type. ++ * 2 plane YCbCr MSB aligned ++ * index 0 = Y plane, [15:0] Y:x [10:6] little endian ++ * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian + */ -+struct drm_ctx_res { -+ int count; -+ struct drm_ctx *contexts; -+}; ++#define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */ + +/* -+ * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type. ++ * 2 plane YCbCr MSB aligned ++ * index 0 = Y plane, [15:0] Y:x [12:4] little endian ++ * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian + */ -+struct drm_draw { -+ drm_drawable_t handle; -+}; ++#define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */ + +/* -+ * DRM_IOCTL_UPDATE_DRAW ioctl argument type. ++ * 2 plane YCbCr MSB aligned ++ * index 0 = Y plane, [15:0] Y little endian ++ * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian + */ -+typedef enum { -+ DRM_DRAWABLE_CLIPRECTS -+} drm_drawable_info_type_t; ++#define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */ + -+struct drm_update_draw { -+ drm_drawable_t handle; -+ unsigned int type; -+ unsigned int num; -+ unsigned long long data; -+}; ++/* 3 plane non-subsampled (444) YCbCr ++ * 16 bits per component, but only 10 bits are used and 6 bits are padded ++ * index 0: Y plane, [15:0] Y:x [10:6] little endian ++ * index 1: Cb plane, [15:0] Cb:x [10:6] little endian ++ * index 2: Cr plane, [15:0] Cr:x [10:6] little endian ++ */ ++#define DRM_FORMAT_Q410 fourcc_code('Q', '4', '1', '0') ++ ++/* 3 plane non-subsampled (444) YCrCb ++ * 16 bits per component, but only 10 bits are used and 6 bits are padded ++ * index 0: Y plane, [15:0] Y:x [10:6] little endian ++ * index 1: Cr plane, [15:0] Cr:x [10:6] little endian ++ * index 2: Cb plane, [15:0] Cb:x [10:6] little endian ++ */ ++#define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1') + +/* -+ * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type. ++ * 3 plane YCbCr ++ * index 0: Y plane, [7:0] Y ++ * index 1: Cb plane, [7:0] Cb ++ * index 2: Cr plane, [7:0] Cr ++ * or ++ * index 1: Cr plane, [7:0] Cr ++ * index 2: Cb plane, [7:0] Cb + */ -+struct drm_auth { -+ drm_magic_t magic; -+}; ++#define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */ ++#define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */ ++#define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */ ++#define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */ ++#define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */ ++#define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */ ++#define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */ ++#define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */ ++#define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */ ++#define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */ ++ + +/* -+ * DRM_IOCTL_IRQ_BUSID ioctl argument type. ++ * Format Modifiers: + * -+ * \sa drmGetInterruptFromBusID(). ++ * Format modifiers describe, typically, a re-ordering or modification ++ * of the data in a plane of an FB. This can be used to express tiled/ ++ * swizzled formats, or compression, or a combination of the two. ++ * ++ * The upper 8 bits of the format modifier are a vendor-id as assigned ++ * below. The lower 56 bits are assigned as vendor sees fit. + */ -+struct drm_irq_busid { -+ int irq; /**< IRQ number */ -+ int busnum; /**< bus number */ -+ int devnum; /**< device number */ -+ int funcnum; /**< function number */ -+}; + -+enum drm_vblank_seq_type { -+ _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */ -+ _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */ -+ /* bits 1-6 are reserved for high crtcs */ -+ _DRM_VBLANK_HIGH_CRTC_MASK = 0x0000003e, -+ _DRM_VBLANK_EVENT = 0x4000000, /**< Send event instead of blocking */ -+ _DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */ -+ _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */ -+ _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */ -+ _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking, unsupported */ -+}; -+#define _DRM_VBLANK_HIGH_CRTC_SHIFT 1 ++/* Vendor Ids: */ ++#define DRM_FORMAT_MOD_VENDOR_NONE 0 ++#define DRM_FORMAT_MOD_VENDOR_INTEL 0x01 ++#define DRM_FORMAT_MOD_VENDOR_AMD 0x02 ++#define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03 ++#define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04 ++#define DRM_FORMAT_MOD_VENDOR_QCOM 0x05 ++#define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06 ++#define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07 ++#define DRM_FORMAT_MOD_VENDOR_ARM 0x08 ++#define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09 ++#define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a + -+#define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE) -+#define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT | _DRM_VBLANK_SIGNAL | \ -+ _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS) ++/* add more to the end as needed */ + -+struct drm_wait_vblank_request { -+ enum drm_vblank_seq_type type; -+ unsigned int sequence; -+ unsigned long signal; -+}; ++#define DRM_FORMAT_RESERVED ((1ULL << 56) - 1) + -+struct drm_wait_vblank_reply { -+ enum drm_vblank_seq_type type; -+ unsigned int sequence; -+ long tval_sec; -+ long tval_usec; -+}; ++#define fourcc_mod_get_vendor(modifier) \ ++ (((modifier) >> 56) & 0xff) ++ ++#define fourcc_mod_is_vendor(modifier, vendor) \ ++ (fourcc_mod_get_vendor(modifier) == DRM_FORMAT_MOD_VENDOR_## vendor) ++ ++#define fourcc_mod_code(vendor, val) \ ++ ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL)) + +/* -+ * DRM_IOCTL_WAIT_VBLANK ioctl argument type. ++ * Format Modifier tokens: + * -+ * \sa drmWaitVBlank(). ++ * When adding a new token please document the layout with a code comment, ++ * similar to the fourcc codes above. drm_fourcc.h is considered the ++ * authoritative source for all of these. ++ * ++ * Generic modifier names: ++ * ++ * DRM_FORMAT_MOD_GENERIC_* definitions are used to provide vendor-neutral names ++ * for layouts which are common across multiple vendors. To preserve ++ * compatibility, in cases where a vendor-specific definition already exists and ++ * a generic name for it is desired, the common name is a purely symbolic alias ++ * and must use the same numerical value as the original definition. ++ * ++ * Note that generic names should only be used for modifiers which describe ++ * generic layouts (such as pixel re-ordering), which may have ++ * independently-developed support across multiple vendors. ++ * ++ * In future cases where a generic layout is identified before merging with a ++ * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor ++ * 'NONE' could be considered. This should only be for obvious, exceptional ++ * cases to avoid polluting the 'GENERIC' namespace with modifiers which only ++ * apply to a single vendor. ++ * ++ * Generic names should not be used for cases where multiple hardware vendors ++ * have implementations of the same standardised compression scheme (such as ++ * AFBC). In those cases, all implementations should use the same format ++ * modifier(s), reflecting the vendor of the standard. + */ -+union drm_wait_vblank { -+ struct drm_wait_vblank_request request; -+ struct drm_wait_vblank_reply reply; -+}; + -+#define _DRM_PRE_MODESET 1 -+#define _DRM_POST_MODESET 2 ++#define DRM_FORMAT_MOD_GENERIC_16_16_TILE DRM_FORMAT_MOD_SAMSUNG_16_16_TILE + +/* -+ * DRM_IOCTL_MODESET_CTL ioctl argument type ++ * Invalid Modifier + * -+ * \sa drmModesetCtl(). ++ * This modifier can be used as a sentinel to terminate the format modifiers ++ * list, or to initialize a variable with an invalid modifier. It might also be ++ * used to report an error back to userspace for certain APIs. + */ -+struct drm_modeset_ctl { -+ __u32 crtc; -+ __u32 cmd; -+}; ++#define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED) + +/* -+ * DRM_IOCTL_AGP_ENABLE ioctl argument type. ++ * Linear Layout + * -+ * \sa drmAgpEnable(). ++ * Just plain linear layout. Note that this is different from no specifying any ++ * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl), ++ * which tells the driver to also take driver-internal information into account ++ * and so might actually result in a tiled framebuffer. + */ -+struct drm_agp_mode { -+ unsigned long mode; /**< AGP mode */ -+}; ++#define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0) + +/* -+ * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type. ++ * Deprecated: use DRM_FORMAT_MOD_LINEAR instead + * -+ * \sa drmAgpAlloc() and drmAgpFree(). ++ * The "none" format modifier doesn't actually mean that the modifier is ++ * implicit, instead it means that the layout is linear. Whether modifiers are ++ * used is out-of-band information carried in an API-specific way (e.g. in a ++ * flag for drm_mode_fb_cmd2). + */ -+struct drm_agp_buffer { -+ unsigned long size; /**< In bytes -- will round to page boundary */ -+ unsigned long handle; /**< Used for binding / unbinding */ -+ unsigned long type; /**< Type of memory to allocate */ -+ unsigned long physical; /**< Physical used by i810 */ -+}; ++#define DRM_FORMAT_MOD_NONE 0 ++ ++/* Intel framebuffer modifiers */ + +/* -+ * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type. ++ * Intel X-tiling layout + * -+ * \sa drmAgpBind() and drmAgpUnbind(). ++ * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) ++ * in row-major layout. Within the tile bytes are laid out row-major, with ++ * a platform-dependent stride. On top of that the memory can apply ++ * platform-depending swizzling of some higher address bits into bit6. ++ * ++ * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets. ++ * On earlier platforms the is highly platforms specific and not useful for ++ * cross-driver sharing. It exists since on a given platform it does uniquely ++ * identify the layout in a simple way for i915-specific userspace, which ++ * facilitated conversion of userspace to modifiers. Additionally the exact ++ * format on some really old platforms is not known. + */ -+struct drm_agp_binding { -+ unsigned long handle; /**< From drm_agp_buffer */ -+ unsigned long offset; /**< In bytes -- will round to page boundary */ -+}; ++#define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1) + +/* -+ * DRM_IOCTL_AGP_INFO ioctl argument type. ++ * Intel Y-tiling layout + * -+ * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(), -+ * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(), -+ * drmAgpVendorId() and drmAgpDeviceId(). ++ * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) ++ * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes) ++ * chunks column-major, with a platform-dependent height. On top of that the ++ * memory can apply platform-depending swizzling of some higher address bits ++ * into bit6. ++ * ++ * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets. ++ * On earlier platforms the is highly platforms specific and not useful for ++ * cross-driver sharing. It exists since on a given platform it does uniquely ++ * identify the layout in a simple way for i915-specific userspace, which ++ * facilitated conversion of userspace to modifiers. Additionally the exact ++ * format on some really old platforms is not known. + */ -+struct drm_agp_info { -+ int agp_version_major; -+ int agp_version_minor; -+ unsigned long mode; -+ unsigned long aperture_base; /* physical address */ -+ unsigned long aperture_size; /* bytes */ -+ unsigned long memory_allowed; /* bytes */ -+ unsigned long memory_used; -+ -+ /* PCI information */ -+ unsigned short id_vendor; -+ unsigned short id_device; -+}; ++#define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2) + +/* -+ * DRM_IOCTL_SG_ALLOC ioctl argument type. ++ * Intel Yf-tiling layout ++ * ++ * This is a tiled layout using 4Kb tiles in row-major layout. ++ * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which ++ * are arranged in four groups (two wide, two high) with column-major layout. ++ * Each group therefore consits out of four 256 byte units, which are also laid ++ * out as 2x2 column-major. ++ * 256 byte units are made out of four 64 byte blocks of pixels, producing ++ * either a square block or a 2:1 unit. ++ * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width ++ * in pixel depends on the pixel depth. + */ -+struct drm_scatter_gather { -+ unsigned long size; /**< In bytes -- will round to page boundary */ -+ unsigned long handle; /**< Used for mapping / unmapping */ -+}; ++#define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3) + +/* -+ * DRM_IOCTL_SET_VERSION ioctl argument type. ++ * Intel color control surface (CCS) for render compression ++ * ++ * The framebuffer format must be one of the 8:8:8:8 RGB formats. ++ * The main surface will be plane index 0 and must be Y/Yf-tiled, ++ * the CCS will be plane index 1. ++ * ++ * Each CCS tile matches a 1024x512 pixel area of the main surface. ++ * To match certain aspects of the 3D hardware the CCS is ++ * considered to be made up of normal 128Bx32 Y tiles, Thus ++ * the CCS pitch must be specified in multiples of 128 bytes. ++ * ++ * In reality the CCS tile appears to be a 64Bx64 Y tile, composed ++ * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks. ++ * But that fact is not relevant unless the memory is accessed ++ * directly. + */ -+struct drm_set_version { -+ int drm_di_major; -+ int drm_di_minor; -+ int drm_dd_major; -+ int drm_dd_minor; -+}; -+ -+/* DRM_IOCTL_GEM_CLOSE ioctl argument type */ -+struct drm_gem_close { -+ /** Handle of the object to be closed. */ -+ __u32 handle; -+ __u32 pad; -+}; -+ -+/* DRM_IOCTL_GEM_FLINK ioctl argument type */ -+struct drm_gem_flink { -+ /** Handle for the object being named */ -+ __u32 handle; -+ -+ /** Returned global name */ -+ __u32 name; -+}; -+ -+/* DRM_IOCTL_GEM_OPEN ioctl argument type */ -+struct drm_gem_open { -+ /** Name of object being opened */ -+ __u32 name; ++#define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4) ++#define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5) + -+ /** Returned handle for the object */ -+ __u32 handle; ++/* ++ * Intel color control surfaces (CCS) for Gen-12 render compression. ++ * ++ * The main surface is Y-tiled and at plane index 0, the CCS is linear and ++ * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in ++ * main surface. In other words, 4 bits in CCS map to a main surface cache ++ * line pair. The main surface pitch is required to be a multiple of four ++ * Y-tile widths. ++ */ ++#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6) + -+ /** Returned size of the object */ -+ __u64 size; -+}; ++/* ++ * Intel color control surfaces (CCS) for Gen-12 media compression ++ * ++ * The main surface is Y-tiled and at plane index 0, the CCS is linear and ++ * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in ++ * main surface. In other words, 4 bits in CCS map to a main surface cache ++ * line pair. The main surface pitch is required to be a multiple of four ++ * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the ++ * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces, ++ * planes 2 and 3 for the respective CCS. ++ */ ++#define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7) + -+/** -+ * DRM_CAP_DUMB_BUFFER ++/* ++ * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render ++ * compression. + * -+ * If set to 1, the driver supports creating dumb buffers via the -+ * &DRM_IOCTL_MODE_CREATE_DUMB ioctl. ++ * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear ++ * and at index 1. The clear color is stored at index 2, and the pitch should ++ * be ignored. The clear color structure is 256 bits. The first 128 bits ++ * represents Raw Clear Color Red, Green, Blue and Alpha color each represented ++ * by 32 bits. The raw clear color is consumed by the 3d engine and generates ++ * the converted clear color of size 64 bits. The first 32 bits store the Lower ++ * Converted Clear Color value and the next 32 bits store the Higher Converted ++ * Clear Color value when applicable. The Converted Clear Color values are ++ * consumed by the DE. The last 64 bits are used to store Color Discard Enable ++ * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line ++ * corresponds to an area of 4x1 tiles in the main surface. The main surface ++ * pitch is required to be a multiple of 4 tile widths. + */ -+#define DRM_CAP_DUMB_BUFFER 0x1 -+/** -+ * DRM_CAP_VBLANK_HIGH_CRTC ++#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8) ++ ++/* ++ * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks + * -+ * If set to 1, the kernel supports specifying a :ref:`CRTC index` -+ * in the high bits of &drm_wait_vblank_request.type. ++ * Macroblocks are laid in a Z-shape, and each pixel data is following the ++ * standard NV12 style. ++ * As for NV12, an image is the result of two frame buffers: one for Y, ++ * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer). ++ * Alignment requirements are (for each buffer): ++ * - multiple of 128 pixels for the width ++ * - multiple of 32 pixels for the height + * -+ * Starting kernel version 2.6.39, this capability is always set to 1. ++ * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html + */ -+#define DRM_CAP_VBLANK_HIGH_CRTC 0x2 -+/** -+ * DRM_CAP_DUMB_PREFERRED_DEPTH ++#define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1) ++ ++/* ++ * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks + * -+ * The preferred bit depth for dumb buffers. ++ * This is a simple tiled layout using tiles of 16x16 pixels in a row-major ++ * layout. For YCbCr formats Cb/Cr components are taken in such a way that ++ * they correspond to their 16x16 luma block. ++ */ ++#define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE fourcc_mod_code(SAMSUNG, 2) ++ ++/* ++ * Qualcomm Compressed Format + * -+ * The bit depth is the number of bits used to indicate the color of a single -+ * pixel excluding any padding. This is different from the number of bits per -+ * pixel. For instance, XRGB8888 has a bit depth of 24 but has 32 bits per -+ * pixel. ++ * Refers to a compressed variant of the base format that is compressed. ++ * Implementation may be platform and base-format specific. + * -+ * Note that this preference only applies to dumb buffers, it's irrelevant for -+ * other types of buffers. ++ * Each macrotile consists of m x n (mostly 4 x 4) tiles. ++ * Pixel data pitch/stride is aligned with macrotile width. ++ * Pixel data height is aligned with macrotile height. ++ * Entire pixel data buffer is aligned with 4k(bytes). + */ -+#define DRM_CAP_DUMB_PREFERRED_DEPTH 0x3 -+/** -+ * DRM_CAP_DUMB_PREFER_SHADOW -+ * -+ * If set to 1, the driver prefers userspace to render to a shadow buffer -+ * instead of directly rendering to a dumb buffer. For best speed, userspace -+ * should do streaming ordered memory copies into the dumb buffer and never -+ * read from it. ++#define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1) ++ ++/* Vivante framebuffer modifiers */ ++ ++/* ++ * Vivante 4x4 tiling layout + * -+ * Note that this preference only applies to dumb buffers, it's irrelevant for -+ * other types of buffers. ++ * This is a simple tiled layout using tiles of 4x4 pixels in a row-major ++ * layout. + */ -+#define DRM_CAP_DUMB_PREFER_SHADOW 0x4 -+/** -+ * DRM_CAP_PRIME ++#define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1) ++ ++/* ++ * Vivante 64x64 super-tiling layout + * -+ * Bitfield of supported PRIME sharing capabilities. See &DRM_PRIME_CAP_IMPORT -+ * and &DRM_PRIME_CAP_EXPORT. ++ * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile ++ * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row- ++ * major layout. + * -+ * PRIME buffers are exposed as dma-buf file descriptors. See -+ * Documentation/gpu/drm-mm.rst, section "PRIME Buffer Sharing". ++ * For more information: see ++ * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling + */ -+#define DRM_CAP_PRIME 0x5 -+/** -+ * DRM_PRIME_CAP_IMPORT ++#define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2) ++ ++/* ++ * Vivante 4x4 tiling layout for dual-pipe + * -+ * If this bit is set in &DRM_CAP_PRIME, the driver supports importing PRIME -+ * buffers via the &DRM_IOCTL_PRIME_FD_TO_HANDLE ioctl. -+ */ -+#define DRM_PRIME_CAP_IMPORT 0x1 -+/** -+ * DRM_PRIME_CAP_EXPORT -+ * -+ * If this bit is set in &DRM_CAP_PRIME, the driver supports exporting PRIME -+ * buffers via the &DRM_IOCTL_PRIME_HANDLE_TO_FD ioctl. ++ * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a ++ * different base address. Offsets from the base addresses are therefore halved ++ * compared to the non-split tiled layout. + */ -+#define DRM_PRIME_CAP_EXPORT 0x2 -+/** -+ * DRM_CAP_TIMESTAMP_MONOTONIC -+ * -+ * If set to 0, the kernel will report timestamps with ``CLOCK_REALTIME`` in -+ * struct drm_event_vblank. If set to 1, the kernel will report timestamps with -+ * ``CLOCK_MONOTONIC``. See ``clock_gettime(2)`` for the definition of these -+ * clocks. ++#define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3) ++ ++/* ++ * Vivante 64x64 super-tiling layout for dual-pipe + * -+ * Starting from kernel version 2.6.39, the default value for this capability -+ * is 1. Starting kernel version 4.15, this capability is always set to 1. ++ * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile ++ * starts at a different base address. Offsets from the base addresses are ++ * therefore halved compared to the non-split super-tiled layout. + */ -+#define DRM_CAP_TIMESTAMP_MONOTONIC 0x6 -+/** -+ * DRM_CAP_ASYNC_PAGE_FLIP ++#define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4) ++ ++/* NVIDIA frame buffer modifiers */ ++ ++/* ++ * Tegra Tiled Layout, used by Tegra 2, 3 and 4. + * -+ * If set to 1, the driver supports &DRM_MODE_PAGE_FLIP_ASYNC. ++ * Pixels are arranged in simple tiles of 16 x 16 bytes. + */ -+#define DRM_CAP_ASYNC_PAGE_FLIP 0x7 -+/** -+ * DRM_CAP_CURSOR_WIDTH ++#define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1) ++ ++/* ++ * Generalized Block Linear layout, used by desktop GPUs starting with NV50/G80, ++ * and Tegra GPUs starting with Tegra K1. + * -+ * The ``CURSOR_WIDTH`` and ``CURSOR_HEIGHT`` capabilities return a valid -+ * width x height combination for the hardware cursor. The intention is that a -+ * hardware agnostic userspace can query a cursor plane size to use. ++ * Pixels are arranged in Groups of Bytes (GOBs). GOB size and layout varies ++ * based on the architecture generation. GOBs themselves are then arranged in ++ * 3D blocks, with the block dimensions (in terms of GOBs) always being a power ++ * of two, and hence expressible as their log2 equivalent (E.g., "2" represents ++ * a block depth or height of "4"). + * -+ * Note that the cross-driver contract is to merely return a valid size; -+ * drivers are free to attach another meaning on top, eg. i915 returns the -+ * maximum plane size. -+ */ -+#define DRM_CAP_CURSOR_WIDTH 0x8 -+/** -+ * DRM_CAP_CURSOR_HEIGHT ++ * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format ++ * in full detail. + * -+ * See &DRM_CAP_CURSOR_WIDTH. -+ */ -+#define DRM_CAP_CURSOR_HEIGHT 0x9 -+/** -+ * DRM_CAP_ADDFB2_MODIFIERS ++ * Macro ++ * Bits Param Description ++ * ---- ----- ----------------------------------------------------------------- + * -+ * If set to 1, the driver supports supplying modifiers in the -+ * &DRM_IOCTL_MODE_ADDFB2 ioctl. -+ */ -+#define DRM_CAP_ADDFB2_MODIFIERS 0x10 -+/** -+ * DRM_CAP_PAGE_FLIP_TARGET ++ * 3:0 h log2(height) of each block, in GOBs. Placed here for ++ * compatibility with the existing ++ * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers. + * -+ * If set to 1, the driver supports the &DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE and -+ * &DRM_MODE_PAGE_FLIP_TARGET_RELATIVE flags in -+ * &drm_mode_crtc_page_flip_target.flags for the &DRM_IOCTL_MODE_PAGE_FLIP -+ * ioctl. -+ */ -+#define DRM_CAP_PAGE_FLIP_TARGET 0x11 -+/** -+ * DRM_CAP_CRTC_IN_VBLANK_EVENT ++ * 4:4 - Must be 1, to indicate block-linear layout. Necessary for ++ * compatibility with the existing ++ * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers. + * -+ * If set to 1, the kernel supports reporting the CRTC ID in -+ * &drm_event_vblank.crtc_id for the &DRM_EVENT_VBLANK and -+ * &DRM_EVENT_FLIP_COMPLETE events. ++ * 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block ++ * size). Must be zero. + * -+ * Starting kernel version 4.12, this capability is always set to 1. -+ */ -+#define DRM_CAP_CRTC_IN_VBLANK_EVENT 0x12 -+/** -+ * DRM_CAP_SYNCOBJ ++ * Note there is no log2(width) parameter. Some portions of the ++ * hardware support a block width of two gobs, but it is impractical ++ * to use due to lack of support elsewhere, and has no known ++ * benefits. + * -+ * If set to 1, the driver supports sync objects. See -+ * Documentation/gpu/drm-mm.rst, section "DRM Sync Objects". -+ */ -+#define DRM_CAP_SYNCOBJ 0x13 -+/** -+ * DRM_CAP_SYNCOBJ_TIMELINE ++ * 11:9 - Reserved (To support 2D-array textures with variable array stride ++ * in blocks, specified via log2(tile width in blocks)). Must be ++ * zero. + * -+ * If set to 1, the driver supports timeline operations on sync objects. See -+ * Documentation/gpu/drm-mm.rst, section "DRM Sync Objects". -+ */ -+#define DRM_CAP_SYNCOBJ_TIMELINE 0x14 -+ -+/* DRM_IOCTL_GET_CAP ioctl argument type */ -+struct drm_get_cap { -+ __u64 capability; -+ __u64 value; -+}; -+ -+/** -+ * DRM_CLIENT_CAP_STEREO_3D ++ * 19:12 k Page Kind. This value directly maps to a field in the page ++ * tables of all GPUs >= NV50. It affects the exact layout of bits ++ * in memory and can be derived from the tuple + * -+ * If set to 1, the DRM core will expose the stereo 3D capabilities of the -+ * monitor by advertising the supported 3D layouts in the flags of struct -+ * drm_mode_modeinfo. See ``DRM_MODE_FLAG_3D_*``. ++ * (format, GPU model, compression type, samples per pixel) + * -+ * This capability is always supported for all drivers starting from kernel -+ * version 3.13. -+ */ -+#define DRM_CLIENT_CAP_STEREO_3D 1 -+ -+/** -+ * DRM_CLIENT_CAP_UNIVERSAL_PLANES ++ * Where compression type is defined below. If GPU model were ++ * implied by the format modifier, format, or memory buffer, page ++ * kind would not need to be included in the modifier itself, but ++ * since the modifier should define the layout of the associated ++ * memory buffer independent from any device or other context, it ++ * must be included here. + * -+ * If set to 1, the DRM core will expose all planes (overlay, primary, and -+ * cursor) to userspace. ++ * 21:20 g GOB Height and Page Kind Generation. The height of a GOB changed ++ * starting with Fermi GPUs. Additionally, the mapping between page ++ * kind and bit layout has changed at various points. + * -+ * This capability has been introduced in kernel version 3.15. Starting from -+ * kernel version 3.17, this capability is always supported for all drivers. -+ */ -+#define DRM_CLIENT_CAP_UNIVERSAL_PLANES 2 -+ -+/** -+ * DRM_CLIENT_CAP_ATOMIC ++ * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping ++ * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping ++ * 2 = Gob Height 8, Turing+ Page Kind mapping ++ * 3 = Reserved for future use. + * -+ * If set to 1, the DRM core will expose atomic properties to userspace. This -+ * implicitly enables &DRM_CLIENT_CAP_UNIVERSAL_PLANES and -+ * &DRM_CLIENT_CAP_ASPECT_RATIO. ++ * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further ++ * bit remapping step that occurs at an even lower level than the ++ * page kind and block linear swizzles. This causes the layout of ++ * surfaces mapped in those SOC's GPUs to be incompatible with the ++ * equivalent mapping on other GPUs in the same system. + * -+ * If the driver doesn't support atomic mode-setting, enabling this capability -+ * will fail with -EOPNOTSUPP. ++ * 0 = Tegra K1 - Tegra Parker/TX2 Layout. ++ * 1 = Desktop GPU and Tegra Xavier+ Layout + * -+ * This capability has been introduced in kernel version 4.0. Starting from -+ * kernel version 4.2, this capability is always supported for atomic-capable -+ * drivers. -+ */ -+#define DRM_CLIENT_CAP_ATOMIC 3 -+ -+/** -+ * DRM_CLIENT_CAP_ASPECT_RATIO ++ * 25:23 c Lossless Framebuffer Compression type. + * -+ * If set to 1, the DRM core will provide aspect ratio information in modes. -+ * See ``DRM_MODE_FLAG_PIC_AR_*``. ++ * 0 = none ++ * 1 = ROP/3D, layout 1, exact compression format implied by Page ++ * Kind field ++ * 2 = ROP/3D, layout 2, exact compression format implied by Page ++ * Kind field ++ * 3 = CDE horizontal ++ * 4 = CDE vertical ++ * 5 = Reserved for future use ++ * 6 = Reserved for future use ++ * 7 = Reserved for future use + * -+ * This capability is always supported for all drivers starting from kernel -+ * version 4.18. ++ * 55:25 - Reserved for future use. Must be zero. + */ -+#define DRM_CLIENT_CAP_ASPECT_RATIO 4 ++#define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \ ++ fourcc_mod_code(NVIDIA, (0x10 | \ ++ ((h) & 0xf) | \ ++ (((k) & 0xff) << 12) | \ ++ (((g) & 0x3) << 20) | \ ++ (((s) & 0x1) << 22) | \ ++ (((c) & 0x7) << 23))) + -+/** -+ * DRM_CLIENT_CAP_WRITEBACK_CONNECTORS ++/* To grandfather in prior block linear format modifiers to the above layout, ++ * the page kind "0", which corresponds to "pitch/linear" and hence is unusable ++ * with block-linear layouts, is remapped within drivers to the value 0xfe, ++ * which corresponds to the "generic" kind used for simple single-sample ++ * uncompressed color formats on Fermi - Volta GPUs. ++ */ ++static __inline__ __u64 ++drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) ++{ ++ if (!(modifier & 0x10) || (modifier & (0xff << 12))) ++ return modifier; ++ else ++ return modifier | (0xfe << 12); ++} ++ ++/* ++ * 16Bx2 Block Linear layout, used by Tegra K1 and later + * -+ * If set to 1, the DRM core will expose special connectors to be used for -+ * writing back to memory the scene setup in the commit. The client must enable -+ * &DRM_CLIENT_CAP_ATOMIC first. ++ * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked ++ * vertically by a power of 2 (1 to 32 GOBs) to form a block. + * -+ * This capability is always supported for atomic-capable drivers starting from -+ * kernel version 4.19. ++ * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape. ++ * ++ * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically. ++ * Valid values are: ++ * ++ * 0 == ONE_GOB ++ * 1 == TWO_GOBS ++ * 2 == FOUR_GOBS ++ * 3 == EIGHT_GOBS ++ * 4 == SIXTEEN_GOBS ++ * 5 == THIRTYTWO_GOBS ++ * ++ * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format ++ * in full detail. + */ -+#define DRM_CLIENT_CAP_WRITEBACK_CONNECTORS 5 -+ -+/* DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */ -+struct drm_set_client_cap { -+ __u64 capability; -+ __u64 value; -+}; ++#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \ ++ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 0, 0, 0, (v)) + -+#define DRM_RDWR O_RDWR -+#define DRM_CLOEXEC O_CLOEXEC -+struct drm_prime_handle { -+ __u32 handle; -+ -+ /** Flags.. only applicable for handle->fd */ -+ __u32 flags; ++#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \ ++ DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0) ++#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \ ++ DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1) ++#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \ ++ DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2) ++#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \ ++ DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3) ++#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \ ++ DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4) ++#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \ ++ DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5) + -+ /** Returned dmabuf file descriptor */ -+ __s32 fd; -+}; ++/* ++ * Some Broadcom modifiers take parameters, for example the number of ++ * vertical lines in the image. Reserve the lower 32 bits for modifier ++ * type, and the next 24 bits for parameters. Top 8 bits are the ++ * vendor code. ++ */ ++#define __fourcc_mod_broadcom_param_shift 8 ++#define __fourcc_mod_broadcom_param_bits 48 ++#define fourcc_mod_broadcom_code(val, params) \ ++ fourcc_mod_code(BROADCOM, ((((__u64)params) << __fourcc_mod_broadcom_param_shift) | val)) ++#define fourcc_mod_broadcom_param(m) \ ++ ((int)(((m) >> __fourcc_mod_broadcom_param_shift) & \ ++ ((1ULL << __fourcc_mod_broadcom_param_bits) - 1))) ++#define fourcc_mod_broadcom_mod(m) \ ++ ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \ ++ __fourcc_mod_broadcom_param_shift)) + -+struct drm_syncobj_create { -+ __u32 handle; -+#define DRM_SYNCOBJ_CREATE_SIGNALED (1 << 0) -+ __u32 flags; -+}; ++/* ++ * Broadcom VC4 "T" format ++ * ++ * This is the primary layout that the V3D GPU can texture from (it ++ * can't do linear). The T format has: ++ * ++ * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4 ++ * pixels at 32 bit depth. ++ * ++ * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually ++ * 16x16 pixels). ++ * ++ * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On ++ * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows ++ * they're (TR, BR, BL, TL), where bottom left is start of memory. ++ * ++ * - an image made of 4k tiles in rows either left-to-right (even rows of 4k ++ * tiles) or right-to-left (odd rows of 4k tiles). ++ */ ++#define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1) + -+struct drm_syncobj_destroy { -+ __u32 handle; -+ __u32 pad; -+}; ++/* ++ * Broadcom SAND format ++ * ++ * This is the native format that the H.264 codec block uses. For VC4 ++ * HVS, it is only valid for H.264 (NV12/21) and RGBA modes. ++ * ++ * The image can be considered to be split into columns, and the ++ * columns are placed consecutively into memory. The width of those ++ * columns can be either 32, 64, 128, or 256 pixels, but in practice ++ * only 128 pixel columns are used. ++ * ++ * The pitch between the start of each column is set to optimally ++ * switch between SDRAM banks. This is passed as the number of lines ++ * of column width in the modifier (we can't use the stride value due ++ * to various core checks that look at it , so you should set the ++ * stride to width*cpp). ++ * ++ * Note that the column height for this format modifier is the same ++ * for all of the planes, assuming that each column contains both Y ++ * and UV. Some SAND-using hardware stores UV in a separate tiled ++ * image from Y to reduce the column height, which is not supported ++ * with these modifiers. ++ */ + -+#define DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_IMPORT_SYNC_FILE (1 << 0) -+#define DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_SYNC_FILE (1 << 0) -+struct drm_syncobj_handle { -+ __u32 handle; -+ __u32 flags; ++#define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \ ++ fourcc_mod_broadcom_code(2, v) ++#define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \ ++ fourcc_mod_broadcom_code(3, v) ++#define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \ ++ fourcc_mod_broadcom_code(4, v) ++#define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \ ++ fourcc_mod_broadcom_code(5, v) + -+ __s32 fd; -+ __u32 pad; -+}; ++#define DRM_FORMAT_MOD_BROADCOM_SAND32 \ ++ DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0) ++#define DRM_FORMAT_MOD_BROADCOM_SAND64 \ ++ DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0) ++#define DRM_FORMAT_MOD_BROADCOM_SAND128 \ ++ DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0) ++#define DRM_FORMAT_MOD_BROADCOM_SAND256 \ ++ DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0) + -+struct drm_syncobj_transfer { -+ __u32 src_handle; -+ __u32 dst_handle; -+ __u64 src_point; -+ __u64 dst_point; -+ __u32 flags; -+ __u32 pad; -+}; ++/* Broadcom UIF format ++ * ++ * This is the common format for the current Broadcom multimedia ++ * blocks, including V3D 3.x and newer, newer video codecs, and ++ * displays. ++ * ++ * The image consists of utiles (64b blocks), UIF blocks (2x2 utiles), ++ * and macroblocks (4x4 UIF blocks). Those 4x4 UIF block groups are ++ * stored in columns, with padding between the columns to ensure that ++ * moving from one column to the next doesn't hit the same SDRAM page ++ * bank. ++ * ++ * To calculate the padding, it is assumed that each hardware block ++ * and the software driving it knows the platform's SDRAM page size, ++ * number of banks, and XOR address, and that it's identical between ++ * all blocks using the format. This tiling modifier will use XOR as ++ * necessary to reduce the padding. If a hardware block can't do XOR, ++ * the assumption is that a no-XOR tiling modifier will be created. ++ */ ++#define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6) + -+#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL (1 << 0) -+#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT (1 << 1) -+#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABLE (1 << 2) /* wait for time point to become available */ -+struct drm_syncobj_wait { -+ __u64 handles; -+ /* absolute timeout */ -+ __s64 timeout_nsec; -+ __u32 count_handles; -+ __u32 flags; -+ __u32 first_signaled; /* only valid when not waiting all */ -+ __u32 pad; -+}; ++/* ++ * Arm Framebuffer Compression (AFBC) modifiers ++ * ++ * AFBC is a proprietary lossless image compression protocol and format. ++ * It provides fine-grained random access and minimizes the amount of data ++ * transferred between IP blocks. ++ * ++ * AFBC has several features which may be supported and/or used, which are ++ * represented using bits in the modifier. Not all combinations are valid, ++ * and different devices or use-cases may support different combinations. ++ * ++ * Further information on the use of AFBC modifiers can be found in ++ * Documentation/gpu/afbc.rst ++ */ + -+struct drm_syncobj_timeline_wait { -+ __u64 handles; -+ /* wait on specific timeline point for every handles*/ -+ __u64 points; -+ /* absolute timeout */ -+ __s64 timeout_nsec; -+ __u32 count_handles; -+ __u32 flags; -+ __u32 first_signaled; /* only valid when not waiting all */ -+ __u32 pad; -+}; ++/* ++ * The top 4 bits (out of the 56 bits alloted for specifying vendor specific ++ * modifiers) denote the category for modifiers. Currently we have three ++ * categories of modifiers ie AFBC, MISC and AFRC. We can have a maximum of ++ * sixteen different categories. ++ */ ++#define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \ ++ fourcc_mod_code(ARM, ((__u64)(__type) << 52) | ((__val) & 0x000fffffffffffffULL)) + ++#define DRM_FORMAT_MOD_ARM_TYPE_AFBC 0x00 ++#define DRM_FORMAT_MOD_ARM_TYPE_MISC 0x01 + -+struct drm_syncobj_array { -+ __u64 handles; -+ __u32 count_handles; -+ __u32 pad; -+}; ++#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) \ ++ DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode) + -+#define DRM_SYNCOBJ_QUERY_FLAGS_LAST_SUBMITTED (1 << 0) /* last available point on timeline syncobj */ -+struct drm_syncobj_timeline_array { -+ __u64 handles; -+ __u64 points; -+ __u32 count_handles; -+ __u32 flags; -+}; ++/* ++ * AFBC superblock size ++ * ++ * Indicates the superblock size(s) used for the AFBC buffer. The buffer ++ * size (in pixels) must be aligned to a multiple of the superblock size. ++ * Four lowest significant bits(LSBs) are reserved for block size. ++ * ++ * Where one superblock size is specified, it applies to all planes of the ++ * buffer (e.g. 16x16, 32x8). When multiple superblock sizes are specified, ++ * the first applies to the Luma plane and the second applies to the Chroma ++ * plane(s). e.g. (32x8_64x4 means 32x8 Luma, with 64x4 Chroma). ++ * Multiple superblock sizes are only valid for multi-plane YCbCr formats. ++ */ ++#define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf ++#define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL) ++#define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL) ++#define AFBC_FORMAT_MOD_BLOCK_SIZE_64x4 (3ULL) ++#define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL) + ++/* ++ * AFBC lossless colorspace transform ++ * ++ * Indicates that the buffer makes use of the AFBC lossless colorspace ++ * transform. ++ */ ++#define AFBC_FORMAT_MOD_YTR (1ULL << 4) + -+/* Query current scanout sequence number */ -+struct drm_crtc_get_sequence { -+ __u32 crtc_id; /* requested crtc_id */ -+ __u32 active; /* return: crtc output is active */ -+ __u64 sequence; /* return: most recent vblank sequence */ -+ __s64 sequence_ns; /* return: most recent time of first pixel out */ -+}; ++/* ++ * AFBC block-split ++ * ++ * Indicates that the payload of each superblock is split. The second ++ * half of the payload is positioned at a predefined offset from the start ++ * of the superblock payload. ++ */ ++#define AFBC_FORMAT_MOD_SPLIT (1ULL << 5) + -+/* Queue event to be delivered at specified sequence. Time stamp marks -+ * when the first pixel of the refresh cycle leaves the display engine -+ * for the display ++/* ++ * AFBC sparse layout ++ * ++ * This flag indicates that the payload of each superblock must be stored at a ++ * predefined position relative to the other superblocks in the same AFBC ++ * buffer. This order is the same order used by the header buffer. In this mode ++ * each superblock is given the same amount of space as an uncompressed ++ * superblock of the particular format would require, rounding up to the next ++ * multiple of 128 bytes in size. + */ -+#define DRM_CRTC_SEQUENCE_RELATIVE 0x00000001 /* sequence is relative to current */ -+#define DRM_CRTC_SEQUENCE_NEXT_ON_MISS 0x00000002 /* Use next sequence if we've missed */ ++#define AFBC_FORMAT_MOD_SPARSE (1ULL << 6) + -+struct drm_crtc_queue_sequence { -+ __u32 crtc_id; -+ __u32 flags; -+ __u64 sequence; /* on input, target sequence. on output, actual sequence */ -+ __u64 user_data; /* user data passed to event */ -+}; ++/* ++ * AFBC copy-block restrict ++ * ++ * Buffers with this flag must obey the copy-block restriction. The restriction ++ * is such that there are no copy-blocks referring across the border of 8x8 ++ * blocks. For the subsampled data the 8x8 limitation is also subsampled. ++ */ ++#define AFBC_FORMAT_MOD_CBR (1ULL << 7) + -+#if defined(__cplusplus) -+} -+#endif ++/* ++ * AFBC tiled layout ++ * ++ * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all ++ * superblocks inside a tile are stored together in memory. 8x8 tiles are used ++ * for pixel formats up to and including 32 bpp while 4x4 tiles are used for ++ * larger bpp formats. The order between the tiles is scan line. ++ * When the tiled layout is used, the buffer size (in pixels) must be aligned ++ * to the tile size. ++ */ ++#define AFBC_FORMAT_MOD_TILED (1ULL << 8) + -+#include "drm_mode.h" ++/* ++ * AFBC solid color blocks ++ * ++ * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth ++ * can be reduced if a whole superblock is a single color. ++ */ ++#define AFBC_FORMAT_MOD_SC (1ULL << 9) + -+#if defined(__cplusplus) -+extern "C" { -+#endif ++/* ++ * AFBC double-buffer ++ * ++ * Indicates that the buffer is allocated in a layout safe for front-buffer ++ * rendering. ++ */ ++#define AFBC_FORMAT_MOD_DB (1ULL << 10) + -+#define DRM_IOCTL_BASE 'd' -+#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr) -+#define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type) -+#define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type) -+#define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type) ++/* ++ * AFBC buffer content hints ++ * ++ * Indicates that the buffer includes per-superblock content hints. ++ */ ++#define AFBC_FORMAT_MOD_BCH (1ULL << 11) + -+#define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version) -+#define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, struct drm_unique) -+#define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, struct drm_auth) -+#define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, struct drm_irq_busid) -+#define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map) -+#define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client) -+#define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats) -+#define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version) -+#define DRM_IOCTL_MODESET_CTL DRM_IOW(0x08, struct drm_modeset_ctl) -+#define DRM_IOCTL_GEM_CLOSE DRM_IOW (0x09, struct drm_gem_close) -+#define DRM_IOCTL_GEM_FLINK DRM_IOWR(0x0a, struct drm_gem_flink) -+#define DRM_IOCTL_GEM_OPEN DRM_IOWR(0x0b, struct drm_gem_open) -+#define DRM_IOCTL_GET_CAP DRM_IOWR(0x0c, struct drm_get_cap) -+#define DRM_IOCTL_SET_CLIENT_CAP DRM_IOW( 0x0d, struct drm_set_client_cap) ++/* AFBC uncompressed storage mode ++ * ++ * Indicates that the buffer is using AFBC uncompressed storage mode. ++ * In this mode all superblock payloads in the buffer use the uncompressed ++ * storage mode, which is usually only used for data which cannot be compressed. ++ * The buffer layout is the same as for AFBC buffers without USM set, this only ++ * affects the storage mode of the individual superblocks. Note that even a ++ * buffer without USM set may use uncompressed storage mode for some or all ++ * superblocks, USM just guarantees it for all. ++ */ ++#define AFBC_FORMAT_MOD_USM (1ULL << 12) + -+#define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique) -+#define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth) -+#define DRM_IOCTL_BLOCK DRM_IOWR(0x12, struct drm_block) -+#define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, struct drm_block) -+#define DRM_IOCTL_CONTROL DRM_IOW( 0x14, struct drm_control) -+#define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map) -+#define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, struct drm_buf_desc) -+#define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, struct drm_buf_desc) -+#define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info) -+#define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, struct drm_buf_map) -+#define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, struct drm_buf_free) ++/* ++ * Arm Fixed-Rate Compression (AFRC) modifiers ++ * ++ * AFRC is a proprietary fixed rate image compression protocol and format, ++ * designed to provide guaranteed bandwidth and memory footprint ++ * reductions in graphics and media use-cases. ++ * ++ * AFRC buffers consist of one or more planes, with the same components ++ * and meaning as an uncompressed buffer using the same pixel format. ++ * ++ * Within each plane, the pixel/luma/chroma values are grouped into ++ * "coding unit" blocks which are individually compressed to a ++ * fixed size (in bytes). All coding units within a given plane of a buffer ++ * store the same number of values, and have the same compressed size. ++ * ++ * The coding unit size is configurable, allowing different rates of compression. ++ * ++ * The start of each AFRC buffer plane must be aligned to an alignment granule which ++ * depends on the coding unit size. ++ * ++ * Coding Unit Size Plane Alignment ++ * ---------------- --------------- ++ * 16 bytes 1024 bytes ++ * 24 bytes 512 bytes ++ * 32 bytes 2048 bytes ++ * ++ * Coding units are grouped into paging tiles. AFRC buffer dimensions must be aligned ++ * to a multiple of the paging tile dimensions. ++ * The dimensions of each paging tile depend on whether the buffer is optimised for ++ * scanline (SCAN layout) or rotated (ROT layout) access. ++ * ++ * Layout Paging Tile Width Paging Tile Height ++ * ------ ----------------- ------------------ ++ * SCAN 16 coding units 4 coding units ++ * ROT 8 coding units 8 coding units ++ * ++ * The dimensions of each coding unit depend on the number of components ++ * in the compressed plane and whether the buffer is optimised for ++ * scanline (SCAN layout) or rotated (ROT layout) access. ++ * ++ * Number of Components in Plane Layout Coding Unit Width Coding Unit Height ++ * ----------------------------- --------- ----------------- ------------------ ++ * 1 SCAN 16 samples 4 samples ++ * Example: 16x4 luma samples in a 'Y' plane ++ * 16x4 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer ++ * ----------------------------- --------- ----------------- ------------------ ++ * 1 ROT 8 samples 8 samples ++ * Example: 8x8 luma samples in a 'Y' plane ++ * 8x8 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer ++ * ----------------------------- --------- ----------------- ------------------ ++ * 2 DONT CARE 8 samples 4 samples ++ * Example: 8x4 chroma pairs in the 'UV' plane of a semi-planar YUV buffer ++ * ----------------------------- --------- ----------------- ------------------ ++ * 3 DONT CARE 4 samples 4 samples ++ * Example: 4x4 pixels in an RGB buffer without alpha ++ * ----------------------------- --------- ----------------- ------------------ ++ * 4 DONT CARE 4 samples 4 samples ++ * Example: 4x4 pixels in an RGB buffer with alpha ++ */ + -+#define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map) ++#define DRM_FORMAT_MOD_ARM_TYPE_AFRC 0x02 + -+#define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map) -+#define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map) ++#define DRM_FORMAT_MOD_ARM_AFRC(__afrc_mode) \ ++ DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFRC, __afrc_mode) + -+#define DRM_IOCTL_SET_MASTER DRM_IO(0x1e) -+#define DRM_IOCTL_DROP_MASTER DRM_IO(0x1f) ++/* ++ * AFRC coding unit size modifier. ++ * ++ * Indicates the number of bytes used to store each compressed coding unit for ++ * one or more planes in an AFRC encoded buffer. The coding unit size for chrominance ++ * is the same for both Cb and Cr, which may be stored in separate planes. ++ * ++ * AFRC_FORMAT_MOD_CU_SIZE_P0 indicates the number of bytes used to store ++ * each compressed coding unit in the first plane of the buffer. For RGBA buffers ++ * this is the only plane, while for semi-planar and fully-planar YUV buffers, ++ * this corresponds to the luma plane. ++ * ++ * AFRC_FORMAT_MOD_CU_SIZE_P12 indicates the number of bytes used to store ++ * each compressed coding unit in the second and third planes in the buffer. ++ * For semi-planar and fully-planar YUV buffers, this corresponds to the chroma plane(s). ++ * ++ * For single-plane buffers, AFRC_FORMAT_MOD_CU_SIZE_P0 must be specified ++ * and AFRC_FORMAT_MOD_CU_SIZE_P12 must be zero. ++ * For semi-planar and fully-planar buffers, both AFRC_FORMAT_MOD_CU_SIZE_P0 and ++ * AFRC_FORMAT_MOD_CU_SIZE_P12 must be specified. ++ */ ++#define AFRC_FORMAT_MOD_CU_SIZE_MASK 0xf ++#define AFRC_FORMAT_MOD_CU_SIZE_16 (1ULL) ++#define AFRC_FORMAT_MOD_CU_SIZE_24 (2ULL) ++#define AFRC_FORMAT_MOD_CU_SIZE_32 (3ULL) + -+#define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx) -+#define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx) -+#define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, struct drm_ctx) -+#define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, struct drm_ctx) -+#define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, struct drm_ctx) -+#define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, struct drm_ctx) -+#define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, struct drm_ctx_res) -+#define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, struct drm_draw) -+#define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, struct drm_draw) -+#define DRM_IOCTL_DMA DRM_IOWR(0x29, struct drm_dma) -+#define DRM_IOCTL_LOCK DRM_IOW( 0x2a, struct drm_lock) -+#define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock) -+#define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock) ++#define AFRC_FORMAT_MOD_CU_SIZE_P0(__afrc_cu_size) (__afrc_cu_size) ++#define AFRC_FORMAT_MOD_CU_SIZE_P12(__afrc_cu_size) ((__afrc_cu_size) << 4) + -+#define DRM_IOCTL_PRIME_HANDLE_TO_FD DRM_IOWR(0x2d, struct drm_prime_handle) -+#define DRM_IOCTL_PRIME_FD_TO_HANDLE DRM_IOWR(0x2e, struct drm_prime_handle) ++/* ++ * AFRC scanline memory layout. ++ * ++ * Indicates if the buffer uses the scanline-optimised layout ++ * for an AFRC encoded buffer, otherwise, it uses the rotation-optimised layout. ++ * The memory layout is the same for all planes. ++ */ ++#define AFRC_FORMAT_MOD_LAYOUT_SCAN (1ULL << 8) + -+#define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30) -+#define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31) -+#define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, struct drm_agp_mode) -+#define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, struct drm_agp_info) -+#define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, struct drm_agp_buffer) -+#define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, struct drm_agp_buffer) -+#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding) -+#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding) ++/* ++ * Arm 16x16 Block U-Interleaved modifier ++ * ++ * This is used by Arm Mali Utgard and Midgard GPUs. It divides the image ++ * into 16x16 pixel blocks. Blocks are stored linearly in order, but pixels ++ * in the block are reordered. ++ */ ++#define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED \ ++ DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL) + -+#define DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather) -+#define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather) ++/* ++ * Allwinner tiled modifier ++ * ++ * This tiling mode is implemented by the VPU found on all Allwinner platforms, ++ * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3 ++ * planes. ++ * ++ * With this tiling, the luminance samples are disposed in tiles representing ++ * 32x32 pixels and the chrominance samples in tiles representing 32x64 pixels. ++ * The pixel order in each tile is linear and the tiles are disposed linearly, ++ * both in row-major order. ++ */ ++#define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1) + -+#define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank) ++/* ++ * Amlogic Video Framebuffer Compression modifiers ++ * ++ * Amlogic uses a proprietary lossless image compression protocol and format ++ * for their hardware video codec accelerators, either video decoders or ++ * video input encoders. ++ * ++ * It considerably reduces memory bandwidth while writing and reading ++ * frames in memory. ++ * ++ * The underlying storage is considered to be 3 components, 8bit or 10-bit ++ * per component YCbCr 420, single plane : ++ * - DRM_FORMAT_YUV420_8BIT ++ * - DRM_FORMAT_YUV420_10BIT ++ * ++ * The first 8 bits of the mode defines the layout, then the following 8 bits ++ * defines the options changing the layout. ++ * ++ * Not all combinations are valid, and different SoCs may support different ++ * combinations of layout and options. ++ */ ++#define __fourcc_mod_amlogic_layout_mask 0xff ++#define __fourcc_mod_amlogic_options_shift 8 ++#define __fourcc_mod_amlogic_options_mask 0xff + -+#define DRM_IOCTL_CRTC_GET_SEQUENCE DRM_IOWR(0x3b, struct drm_crtc_get_sequence) -+#define DRM_IOCTL_CRTC_QUEUE_SEQUENCE DRM_IOWR(0x3c, struct drm_crtc_queue_sequence) ++#define DRM_FORMAT_MOD_AMLOGIC_FBC(__layout, __options) \ ++ fourcc_mod_code(AMLOGIC, \ ++ ((__layout) & __fourcc_mod_amlogic_layout_mask) | \ ++ (((__options) & __fourcc_mod_amlogic_options_mask) \ ++ << __fourcc_mod_amlogic_options_shift)) + -+#define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw) ++/* Amlogic FBC Layouts */ + -+#define DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res) -+#define DRM_IOCTL_MODE_GETCRTC DRM_IOWR(0xA1, struct drm_mode_crtc) -+#define DRM_IOCTL_MODE_SETCRTC DRM_IOWR(0xA2, struct drm_mode_crtc) -+#define DRM_IOCTL_MODE_CURSOR DRM_IOWR(0xA3, struct drm_mode_cursor) -+#define DRM_IOCTL_MODE_GETGAMMA DRM_IOWR(0xA4, struct drm_mode_crtc_lut) -+#define DRM_IOCTL_MODE_SETGAMMA DRM_IOWR(0xA5, struct drm_mode_crtc_lut) -+#define DRM_IOCTL_MODE_GETENCODER DRM_IOWR(0xA6, struct drm_mode_get_encoder) -+#define DRM_IOCTL_MODE_GETCONNECTOR DRM_IOWR(0xA7, struct drm_mode_get_connector) -+#define DRM_IOCTL_MODE_ATTACHMODE DRM_IOWR(0xA8, struct drm_mode_mode_cmd) /* deprecated (never worked) */ -+#define DRM_IOCTL_MODE_DETACHMODE DRM_IOWR(0xA9, struct drm_mode_mode_cmd) /* deprecated (never worked) */ ++/* ++ * Amlogic FBC Basic Layout ++ * ++ * The basic layout is composed of: ++ * - a body content organized in 64x32 superblocks with 4096 bytes per ++ * superblock in default mode. ++ * - a 32 bytes per 128x64 header block ++ * ++ * This layout is transferrable between Amlogic SoCs supporting this modifier. ++ */ ++#define AMLOGIC_FBC_LAYOUT_BASIC (1ULL) + -+#define DRM_IOCTL_MODE_GETPROPERTY DRM_IOWR(0xAA, struct drm_mode_get_property) -+#define DRM_IOCTL_MODE_SETPROPERTY DRM_IOWR(0xAB, struct drm_mode_connector_set_property) -+#define DRM_IOCTL_MODE_GETPROPBLOB DRM_IOWR(0xAC, struct drm_mode_get_blob) -+#define DRM_IOCTL_MODE_GETFB DRM_IOWR(0xAD, struct drm_mode_fb_cmd) -+#define DRM_IOCTL_MODE_ADDFB DRM_IOWR(0xAE, struct drm_mode_fb_cmd) -+/** -+ * DRM_IOCTL_MODE_RMFB - Remove a framebuffer. ++/* ++ * Amlogic FBC Scatter Memory layout + * -+ * This removes a framebuffer previously added via ADDFB/ADDFB2. The IOCTL -+ * argument is a framebuffer object ID. ++ * Indicates the header contains IOMMU references to the compressed ++ * frames content to optimize memory access and layout. + * -+ * Warning: removing a framebuffer currently in-use on an enabled plane will -+ * disable that plane. The CRTC the plane is linked to may also be disabled -+ * (depending on driver capabilities). ++ * In this mode, only the header memory address is needed, thus the ++ * content memory organization is tied to the current producer ++ * execution and cannot be saved/dumped neither transferrable between ++ * Amlogic SoCs supporting this modifier. ++ * ++ * Due to the nature of the layout, these buffers are not expected to ++ * be accessible by the user-space clients, but only accessible by the ++ * hardware producers and consumers. ++ * ++ * The user-space clients should expect a failure while trying to mmap ++ * the DMA-BUF handle returned by the producer. + */ -+#define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xAF, unsigned int) -+#define DRM_IOCTL_MODE_PAGE_FLIP DRM_IOWR(0xB0, struct drm_mode_crtc_page_flip) -+#define DRM_IOCTL_MODE_DIRTYFB DRM_IOWR(0xB1, struct drm_mode_fb_dirty_cmd) ++#define AMLOGIC_FBC_LAYOUT_SCATTER (2ULL) + -+#define DRM_IOCTL_MODE_CREATE_DUMB DRM_IOWR(0xB2, struct drm_mode_create_dumb) -+#define DRM_IOCTL_MODE_MAP_DUMB DRM_IOWR(0xB3, struct drm_mode_map_dumb) -+#define DRM_IOCTL_MODE_DESTROY_DUMB DRM_IOWR(0xB4, struct drm_mode_destroy_dumb) -+#define DRM_IOCTL_MODE_GETPLANERESOURCES DRM_IOWR(0xB5, struct drm_mode_get_plane_res) -+#define DRM_IOCTL_MODE_GETPLANE DRM_IOWR(0xB6, struct drm_mode_get_plane) -+#define DRM_IOCTL_MODE_SETPLANE DRM_IOWR(0xB7, struct drm_mode_set_plane) -+#define DRM_IOCTL_MODE_ADDFB2 DRM_IOWR(0xB8, struct drm_mode_fb_cmd2) -+#define DRM_IOCTL_MODE_OBJ_GETPROPERTIES DRM_IOWR(0xB9, struct drm_mode_obj_get_properties) -+#define DRM_IOCTL_MODE_OBJ_SETPROPERTY DRM_IOWR(0xBA, struct drm_mode_obj_set_property) -+#define DRM_IOCTL_MODE_CURSOR2 DRM_IOWR(0xBB, struct drm_mode_cursor2) -+#define DRM_IOCTL_MODE_ATOMIC DRM_IOWR(0xBC, struct drm_mode_atomic) -+#define DRM_IOCTL_MODE_CREATEPROPBLOB DRM_IOWR(0xBD, struct drm_mode_create_blob) -+#define DRM_IOCTL_MODE_DESTROYPROPBLOB DRM_IOWR(0xBE, struct drm_mode_destroy_blob) ++/* Amlogic FBC Layout Options Bit Mask */ + -+#define DRM_IOCTL_SYNCOBJ_CREATE DRM_IOWR(0xBF, struct drm_syncobj_create) -+#define DRM_IOCTL_SYNCOBJ_DESTROY DRM_IOWR(0xC0, struct drm_syncobj_destroy) -+#define DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD DRM_IOWR(0xC1, struct drm_syncobj_handle) -+#define DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE DRM_IOWR(0xC2, struct drm_syncobj_handle) -+#define DRM_IOCTL_SYNCOBJ_WAIT DRM_IOWR(0xC3, struct drm_syncobj_wait) -+#define DRM_IOCTL_SYNCOBJ_RESET DRM_IOWR(0xC4, struct drm_syncobj_array) -+#define DRM_IOCTL_SYNCOBJ_SIGNAL DRM_IOWR(0xC5, struct drm_syncobj_array) ++/* ++ * Amlogic FBC Memory Saving mode ++ * ++ * Indicates the storage is packed when pixel size is multiple of word ++ * boudaries, i.e. 8bit should be stored in this mode to save allocation ++ * memory. ++ * ++ * This mode reduces body layout to 3072 bytes per 64x32 superblock with ++ * the basic layout and 3200 bytes per 64x32 superblock combined with ++ * the scatter layout. ++ */ ++#define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0) + -+#define DRM_IOCTL_MODE_CREATE_LEASE DRM_IOWR(0xC6, struct drm_mode_create_lease) -+#define DRM_IOCTL_MODE_LIST_LESSEES DRM_IOWR(0xC7, struct drm_mode_list_lessees) -+#define DRM_IOCTL_MODE_GET_LEASE DRM_IOWR(0xC8, struct drm_mode_get_lease) -+#define DRM_IOCTL_MODE_REVOKE_LEASE DRM_IOWR(0xC9, struct drm_mode_revoke_lease) ++/* ++ * AMD modifiers ++ * ++ * Memory layout: ++ * ++ * without DCC: ++ * - main surface ++ * ++ * with DCC & without DCC_RETILE: ++ * - main surface in plane 0 ++ * - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set) ++ * ++ * with DCC & DCC_RETILE: ++ * - main surface in plane 0 ++ * - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned) ++ * - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned) ++ * ++ * For multi-plane formats the above surfaces get merged into one plane for ++ * each format plane, based on the required alignment only. ++ * ++ * Bits Parameter Notes ++ * ----- ------------------------ --------------------------------------------- ++ * ++ * 7:0 TILE_VERSION Values are AMD_FMT_MOD_TILE_VER_* ++ * 12:8 TILE Values are AMD_FMT_MOD_TILE__* ++ * 13 DCC ++ * 14 DCC_RETILE ++ * 15 DCC_PIPE_ALIGN ++ * 16 DCC_INDEPENDENT_64B ++ * 17 DCC_INDEPENDENT_128B ++ * 19:18 DCC_MAX_COMPRESSED_BLOCK Values are AMD_FMT_MOD_DCC_BLOCK_* ++ * 20 DCC_CONSTANT_ENCODE ++ * 23:21 PIPE_XOR_BITS Only for some chips ++ * 26:24 BANK_XOR_BITS Only for some chips ++ * 29:27 PACKERS Only for some chips ++ * 32:30 RB Only for some chips ++ * 35:33 PIPE Only for some chips ++ * 55:36 - Reserved for future use, must be zero ++ */ ++#define AMD_FMT_MOD fourcc_mod_code(AMD, 0) + -+#define DRM_IOCTL_SYNCOBJ_TIMELINE_WAIT DRM_IOWR(0xCA, struct drm_syncobj_timeline_wait) -+#define DRM_IOCTL_SYNCOBJ_QUERY DRM_IOWR(0xCB, struct drm_syncobj_timeline_array) -+#define DRM_IOCTL_SYNCOBJ_TRANSFER DRM_IOWR(0xCC, struct drm_syncobj_transfer) -+#define DRM_IOCTL_SYNCOBJ_TIMELINE_SIGNAL DRM_IOWR(0xCD, struct drm_syncobj_timeline_array) ++#define IS_AMD_FMT_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_AMD) + -+#define DRM_IOCTL_MODE_GETFB2 DRM_IOWR(0xCE, struct drm_mode_fb_cmd2) ++/* Reserve 0 for GFX8 and older */ ++#define AMD_FMT_MOD_TILE_VER_GFX9 1 ++#define AMD_FMT_MOD_TILE_VER_GFX10 2 ++#define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3 + +/* -+ * Device specific ioctls should only be in their respective headers -+ * The device specific ioctl range is from 0x40 to 0x9f. -+ * Generic IOCTLS restart at 0xA0. -+ * -+ * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and -+ * drmCommandReadWrite(). ++ * 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical ++ * version. + */ -+#define DRM_COMMAND_BASE 0x40 -+#define DRM_COMMAND_END 0xA0 ++#define AMD_FMT_MOD_TILE_GFX9_64K_S 9 + +/* -+ * Header for events written back to userspace on the drm fd. The -+ * type defines the type of event, the length specifies the total -+ * length of the event (including the header), and user_data is -+ * typically a 64 bit value passed with the ioctl that triggered the -+ * event. A read on the drm fd will always only return complete -+ * events, that is, if for example the read buffer is 100 bytes, and -+ * there are two 64 byte events pending, only one will be returned. -+ * -+ * Event types 0 - 0x7fffffff are generic drm events, 0x80000000 and -+ * up are chipset specific. ++ * 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has ++ * GFX9 as canonical version. + */ -+struct drm_event { -+ __u32 type; -+ __u32 length; -+}; ++#define AMD_FMT_MOD_TILE_GFX9_64K_D 10 ++#define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25 ++#define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26 ++#define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27 + -+#define DRM_EVENT_VBLANK 0x01 -+#define DRM_EVENT_FLIP_COMPLETE 0x02 -+#define DRM_EVENT_CRTC_SEQUENCE 0x03 ++#define AMD_FMT_MOD_DCC_BLOCK_64B 0 ++#define AMD_FMT_MOD_DCC_BLOCK_128B 1 ++#define AMD_FMT_MOD_DCC_BLOCK_256B 2 + -+struct drm_event_vblank { -+ struct drm_event base; -+ __u64 user_data; -+ __u32 tv_sec; -+ __u32 tv_usec; -+ __u32 sequence; -+ __u32 crtc_id; /* 0 on older kernels that do not support this */ -+}; ++#define AMD_FMT_MOD_TILE_VERSION_SHIFT 0 ++#define AMD_FMT_MOD_TILE_VERSION_MASK 0xFF ++#define AMD_FMT_MOD_TILE_SHIFT 8 ++#define AMD_FMT_MOD_TILE_MASK 0x1F + -+/* Event delivered at sequence. Time stamp marks when the first pixel -+ * of the refresh cycle leaves the display engine for the display ++/* Whether DCC compression is enabled. */ ++#define AMD_FMT_MOD_DCC_SHIFT 13 ++#define AMD_FMT_MOD_DCC_MASK 0x1 ++ ++/* ++ * Whether to include two DCC surfaces, one which is rb & pipe aligned, and ++ * one which is not-aligned. + */ -+struct drm_event_crtc_sequence { -+ struct drm_event base; -+ __u64 user_data; -+ __s64 time_ns; -+ __u64 sequence; -+}; ++#define AMD_FMT_MOD_DCC_RETILE_SHIFT 14 ++#define AMD_FMT_MOD_DCC_RETILE_MASK 0x1 + -+/* typedef area */ -+typedef struct drm_clip_rect drm_clip_rect_t; -+typedef struct drm_drawable_info drm_drawable_info_t; -+typedef struct drm_tex_region drm_tex_region_t; -+typedef struct drm_hw_lock drm_hw_lock_t; -+typedef struct drm_version drm_version_t; -+typedef struct drm_unique drm_unique_t; -+typedef struct drm_list drm_list_t; -+typedef struct drm_block drm_block_t; -+typedef struct drm_control drm_control_t; -+typedef enum drm_map_type drm_map_type_t; -+typedef enum drm_map_flags drm_map_flags_t; -+typedef struct drm_ctx_priv_map drm_ctx_priv_map_t; -+typedef struct drm_map drm_map_t; -+typedef struct drm_client drm_client_t; -+typedef enum drm_stat_type drm_stat_type_t; -+typedef struct drm_stats drm_stats_t; -+typedef enum drm_lock_flags drm_lock_flags_t; -+typedef struct drm_lock drm_lock_t; -+typedef enum drm_dma_flags drm_dma_flags_t; -+typedef struct drm_buf_desc drm_buf_desc_t; -+typedef struct drm_buf_info drm_buf_info_t; -+typedef struct drm_buf_free drm_buf_free_t; -+typedef struct drm_buf_pub drm_buf_pub_t; -+typedef struct drm_buf_map drm_buf_map_t; -+typedef struct drm_dma drm_dma_t; -+typedef union drm_wait_vblank drm_wait_vblank_t; -+typedef struct drm_agp_mode drm_agp_mode_t; -+typedef enum drm_ctx_flags drm_ctx_flags_t; -+typedef struct drm_ctx drm_ctx_t; -+typedef struct drm_ctx_res drm_ctx_res_t; -+typedef struct drm_draw drm_draw_t; -+typedef struct drm_update_draw drm_update_draw_t; -+typedef struct drm_auth drm_auth_t; -+typedef struct drm_irq_busid drm_irq_busid_t; -+typedef enum drm_vblank_seq_type drm_vblank_seq_type_t; ++/* Only set if DCC_RETILE = false */ ++#define AMD_FMT_MOD_DCC_PIPE_ALIGN_SHIFT 15 ++#define AMD_FMT_MOD_DCC_PIPE_ALIGN_MASK 0x1 + -+typedef struct drm_agp_buffer drm_agp_buffer_t; -+typedef struct drm_agp_binding drm_agp_binding_t; -+typedef struct drm_agp_info drm_agp_info_t; -+typedef struct drm_scatter_gather drm_scatter_gather_t; -+typedef struct drm_set_version drm_set_version_t; ++#define AMD_FMT_MOD_DCC_INDEPENDENT_64B_SHIFT 16 ++#define AMD_FMT_MOD_DCC_INDEPENDENT_64B_MASK 0x1 ++#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17 ++#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1 ++#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18 ++#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 ++ ++/* ++ * DCC supports embedding some clear colors directly in the DCC surface. ++ * However, on older GPUs the rendering HW ignores the embedded clear color ++ * and prefers the driver provided color. This necessitates doing a fastclear ++ * eliminate operation before a process transfers control. ++ * ++ * If this bit is set that means the fastclear eliminate is not needed for these ++ * embeddable colors. ++ */ ++#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 20 ++#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_MASK 0x1 ++ ++/* ++ * The below fields are for accounting for per GPU differences. These are only ++ * relevant for GFX9 and later and if the tile field is *_X/_T. ++ * ++ * PIPE_XOR_BITS = always needed ++ * BANK_XOR_BITS = only for TILE_VER_GFX9 ++ * PACKERS = only for TILE_VER_GFX10_RBPLUS ++ * RB = only for TILE_VER_GFX9 & DCC ++ * PIPE = only for TILE_VER_GFX9 & DCC & (DCC_RETILE | DCC_PIPE_ALIGN) ++ */ ++#define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 21 ++#define AMD_FMT_MOD_PIPE_XOR_BITS_MASK 0x7 ++#define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24 ++#define AMD_FMT_MOD_BANK_XOR_BITS_MASK 0x7 ++#define AMD_FMT_MOD_PACKERS_SHIFT 27 ++#define AMD_FMT_MOD_PACKERS_MASK 0x7 ++#define AMD_FMT_MOD_RB_SHIFT 30 ++#define AMD_FMT_MOD_RB_MASK 0x7 ++#define AMD_FMT_MOD_PIPE_SHIFT 33 ++#define AMD_FMT_MOD_PIPE_MASK 0x7 ++ ++#define AMD_FMT_MOD_SET(field, value) \ ++ ((uint64_t)(value) << AMD_FMT_MOD_##field##_SHIFT) ++#define AMD_FMT_MOD_GET(field, value) \ ++ (((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK) ++#define AMD_FMT_MOD_CLEAR(field) \ ++ (~((uint64_t)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT)) + +#if defined(__cplusplus) +} +#endif + -+#endif -diff --git a/third_party/drm/drm/drm_fourcc.h b/third_party/drm/drm/drm_fourcc.h -new file mode 100644 -index 0000000..4ececa8 ---- /dev/null -+++ b/third_party/drm/drm/drm_fourcc.h -@@ -0,0 +1,1377 @@ ++#endif /* DRM_FOURCC_H */ +diff -up firefox-101.0/third_party/drm/drm/drm.h.libwebrtc-screen-cast-sync firefox-101.0/third_party/drm/drm/drm.h +--- firefox-101.0/third_party/drm/drm/drm.h.libwebrtc-screen-cast-sync 2022-05-30 21:33:19.741522076 +0200 ++++ firefox-101.0/third_party/drm/drm/drm.h 2022-05-30 21:33:19.741522076 +0200 +@@ -0,0 +1,1193 @@ +/* -+ * Copyright 2011 Intel Corporation ++ * Header for the Direct Rendering Manager ++ * ++ * Author: Rickard E. (Rik) Faith ++ * ++ * Acknowledgments: ++ * Dec 1999, Richard Henderson , move to generic cmpxchg. ++ */ ++ ++/* ++ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. ++ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. ++ * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), @@ -1255,1365 +1429,1168 @@ index 0000000..4ececa8 + * OTHER DEALINGS IN THE SOFTWARE. + */ + -+#ifndef DRM_FOURCC_H -+#define DRM_FOURCC_H -+ -+#include "drm.h" -+ -+#if defined(__cplusplus) -+extern "C" { -+#endif -+ -+/** -+ * DOC: overview -+ * -+ * In the DRM subsystem, framebuffer pixel formats are described using the -+ * fourcc codes defined in `include/uapi/drm/drm_fourcc.h`. In addition to the -+ * fourcc code, a Format Modifier may optionally be provided, in order to -+ * further describe the buffer's format - for example tiling or compression. -+ * -+ * Format Modifiers -+ * ---------------- -+ * -+ * Format modifiers are used in conjunction with a fourcc code, forming a -+ * unique fourcc:modifier pair. This format:modifier pair must fully define the -+ * format and data layout of the buffer, and should be the only way to describe -+ * that particular buffer. -+ * -+ * Having multiple fourcc:modifier pairs which describe the same layout should -+ * be avoided, as such aliases run the risk of different drivers exposing -+ * different names for the same data format, forcing userspace to understand -+ * that they are aliases. -+ * -+ * Format modifiers may change any property of the buffer, including the number -+ * of planes and/or the required allocation size. Format modifiers are -+ * vendor-namespaced, and as such the relationship between a fourcc code and a -+ * modifier is specific to the modifer being used. For example, some modifiers -+ * may preserve meaning - such as number of planes - from the fourcc code, -+ * whereas others may not. -+ * -+ * Modifiers must uniquely encode buffer layout. In other words, a buffer must -+ * match only a single modifier. A modifier must not be a subset of layouts of -+ * another modifier. For instance, it's incorrect to encode pitch alignment in -+ * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel -+ * aligned modifier. That said, modifiers can have implicit minimal -+ * requirements. -+ * -+ * For modifiers where the combination of fourcc code and modifier can alias, -+ * a canonical pair needs to be defined and used by all drivers. Preferred -+ * combinations are also encouraged where all combinations might lead to -+ * confusion and unnecessarily reduced interoperability. An example for the -+ * latter is AFBC, where the ABGR layouts are preferred over ARGB layouts. -+ * -+ * There are two kinds of modifier users: -+ * -+ * - Kernel and user-space drivers: for drivers it's important that modifiers -+ * don't alias, otherwise two drivers might support the same format but use -+ * different aliases, preventing them from sharing buffers in an efficient -+ * format. -+ * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users -+ * see modifiers as opaque tokens they can check for equality and intersect. -+ * These users musn't need to know to reason about the modifier value -+ * (i.e. they are not expected to extract information out of the modifier). -+ * -+ * Vendors should document their modifier usage in as much detail as -+ * possible, to ensure maximum compatibility across devices, drivers and -+ * applications. -+ * -+ * The authoritative list of format modifier codes is found in -+ * `include/uapi/drm/drm_fourcc.h` -+ */ -+ -+#define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \ -+ ((__u32)(c) << 16) | ((__u32)(d) << 24)) -+ -+#define DRM_FORMAT_BIG_ENDIAN (1U<<31) /* format is big endian instead of little endian */ -+ -+/* Reserve 0 for the invalid format specifier */ -+#define DRM_FORMAT_INVALID 0 -+ -+/* color index */ -+#define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */ -+ -+/* 8 bpp Red */ -+#define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */ -+ -+/* 10 bpp Red */ -+#define DRM_FORMAT_R10 fourcc_code('R', '1', '0', ' ') /* [15:0] x:R 6:10 little endian */ -+ -+/* 12 bpp Red */ -+#define DRM_FORMAT_R12 fourcc_code('R', '1', '2', ' ') /* [15:0] x:R 4:12 little endian */ -+ -+/* 16 bpp Red */ -+#define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */ -+ -+/* 16 bpp RG */ -+#define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */ -+#define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */ -+ -+/* 32 bpp RG */ -+#define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */ -+#define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */ -+ -+/* 8 bpp RGB */ -+#define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */ -+#define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */ -+ -+/* 16 bpp RGB */ -+#define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */ -+#define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */ -+#define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */ -+#define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */ -+ -+#define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */ -+#define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */ -+#define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */ -+#define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */ -+ -+#define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */ -+#define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */ -+#define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */ -+#define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */ -+ -+#define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */ -+#define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */ -+#define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */ -+#define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */ -+ -+#define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */ -+#define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */ -+ -+/* 24 bpp RGB */ -+#define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */ -+#define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */ -+ -+/* 32 bpp RGB */ -+#define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */ -+#define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */ -+#define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */ -+#define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */ -+ -+#define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */ -+#define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */ -+#define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */ -+#define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */ -+ -+#define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */ -+#define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */ -+#define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */ -+#define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */ ++#ifndef _DRM_H_ ++#define _DRM_H_ + -+#define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */ -+#define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */ -+#define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */ -+#define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */ ++#if defined(__linux__) + -+/* 64 bpp RGB */ -+#define DRM_FORMAT_XRGB16161616 fourcc_code('X', 'R', '4', '8') /* [63:0] x:R:G:B 16:16:16:16 little endian */ -+#define DRM_FORMAT_XBGR16161616 fourcc_code('X', 'B', '4', '8') /* [63:0] x:B:G:R 16:16:16:16 little endian */ ++#include ++#include ++typedef unsigned int drm_handle_t; + -+#define DRM_FORMAT_ARGB16161616 fourcc_code('A', 'R', '4', '8') /* [63:0] A:R:G:B 16:16:16:16 little endian */ -+#define DRM_FORMAT_ABGR16161616 fourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 little endian */ ++#else /* One of the BSDs */ + -+/* -+ * Floating point 64bpp RGB -+ * IEEE 754-2008 binary16 half-precision float -+ * [15:0] sign:exponent:mantissa 1:5:10 -+ */ -+#define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */ -+#define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */ ++#include ++#include ++#include ++typedef int8_t __s8; ++typedef uint8_t __u8; ++typedef int16_t __s16; ++typedef uint16_t __u16; ++typedef int32_t __s32; ++typedef uint32_t __u32; ++typedef int64_t __s64; ++typedef uint64_t __u64; ++typedef size_t __kernel_size_t; ++typedef unsigned long drm_handle_t; + -+#define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */ -+#define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */ ++#endif + -+/* -+ * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits -+ * of unused padding per component: -+ */ -+#define DRM_FORMAT_AXBXGXRX106106106106 fourcc_code('A', 'B', '1', '0') /* [63:0] A:x:B:x:G:x:R:x 10:6:10:6:10:6:10:6 little endian */ ++#if defined(__cplusplus) ++extern "C" { ++#endif + -+/* packed YCbCr */ -+#define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */ -+#define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */ -+#define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */ -+#define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */ ++#define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */ ++#define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */ ++#define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */ ++#define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */ + -+#define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */ -+#define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */ -+#define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */ -+#define DRM_FORMAT_VUY101010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */ ++#define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */ ++#define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */ ++#define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD) ++#define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT) ++#define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT)) ++ ++typedef unsigned int drm_context_t; ++typedef unsigned int drm_drawable_t; ++typedef unsigned int drm_magic_t; + +/* -+ * packed Y2xx indicate for each component, xx valid data occupy msb -+ * 16-xx padding occupy lsb ++ * Cliprect. ++ * ++ * \warning: If you change this structure, make sure you change ++ * XF86DRIClipRectRec in the server as well ++ * ++ * \note KW: Actually it's illegal to change either for ++ * backwards-compatibility reasons. + */ -+#define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 10:6:10:6:10:6:10:6 little endian per 2 Y pixels */ -+#define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 12:4:12:4:12:4:12:4 little endian per 2 Y pixels */ -+#define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0] Cr0:Y1:Cb0:Y0 16:16:16:16 little endian per 2 Y pixels */ ++struct drm_clip_rect { ++ unsigned short x1; ++ unsigned short y1; ++ unsigned short x2; ++ unsigned short y2; ++}; + +/* -+ * packed Y4xx indicate for each component, xx valid data occupy msb -+ * 16-xx padding occupy lsb except Y410 ++ * Drawable information. + */ -+#define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 little endian */ -+#define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */ -+#define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 little endian */ -+ -+#define DRM_FORMAT_XVYU2101010 fourcc_code('X', 'V', '3', '0') /* [31:0] X:Cr:Y:Cb 2:10:10:10 little endian */ -+#define DRM_FORMAT_XVYU12_16161616 fourcc_code('X', 'V', '3', '6') /* [63:0] X:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */ -+#define DRM_FORMAT_XVYU16161616 fourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 little endian */ ++struct drm_drawable_info { ++ unsigned int num_rects; ++ struct drm_clip_rect *rects; ++}; + +/* -+ * packed YCbCr420 2x2 tiled formats -+ * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile ++ * Texture region, + */ -+/* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */ -+#define DRM_FORMAT_Y0L0 fourcc_code('Y', '0', 'L', '0') -+/* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */ -+#define DRM_FORMAT_X0L0 fourcc_code('X', '0', 'L', '0') -+ -+/* [63:0] A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */ -+#define DRM_FORMAT_Y0L2 fourcc_code('Y', '0', 'L', '2') -+/* [63:0] X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */ -+#define DRM_FORMAT_X0L2 fourcc_code('X', '0', 'L', '2') ++struct drm_tex_region { ++ unsigned char next; ++ unsigned char prev; ++ unsigned char in_use; ++ unsigned char padding; ++ unsigned int age; ++}; + +/* -+ * 1-plane YUV 4:2:0 -+ * In these formats, the component ordering is specified (Y, followed by U -+ * then V), but the exact Linear layout is undefined. -+ * These formats can only be used with a non-Linear modifier. ++ * Hardware lock. ++ * ++ * The lock structure is a simple cache-line aligned integer. To avoid ++ * processor bus contention on a multiprocessor system, there should not be any ++ * other data stored in the same cache line. + */ -+#define DRM_FORMAT_YUV420_8BIT fourcc_code('Y', 'U', '0', '8') -+#define DRM_FORMAT_YUV420_10BIT fourcc_code('Y', 'U', '1', '0') ++struct drm_hw_lock { ++ __volatile__ unsigned int lock; /**< lock variable */ ++ char padding[60]; /**< Pad to cache line */ ++}; + +/* -+ * 2 plane RGB + A -+ * index 0 = RGB plane, same format as the corresponding non _A8 format has -+ * index 1 = A plane, [7:0] A ++ * DRM_IOCTL_VERSION ioctl argument type. ++ * ++ * \sa drmGetVersion(). + */ -+#define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8') -+#define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8') -+#define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8') -+#define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8') -+#define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8') -+#define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8') -+#define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8') -+#define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8') ++struct drm_version { ++ int version_major; /**< Major version */ ++ int version_minor; /**< Minor version */ ++ int version_patchlevel; /**< Patch level */ ++ __kernel_size_t name_len; /**< Length of name buffer */ ++ char *name; /**< Name of driver */ ++ __kernel_size_t date_len; /**< Length of date buffer */ ++ char *date; /**< User-space buffer to hold date */ ++ __kernel_size_t desc_len; /**< Length of desc buffer */ ++ char *desc; /**< User-space buffer to hold desc */ ++}; + +/* -+ * 2 plane YCbCr -+ * index 0 = Y plane, [7:0] Y -+ * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian -+ * or -+ * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian ++ * DRM_IOCTL_GET_UNIQUE ioctl argument type. ++ * ++ * \sa drmGetBusid() and drmSetBusId(). + */ -+#define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */ -+#define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */ -+#define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */ -+#define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */ -+#define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */ -+#define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */ ++struct drm_unique { ++ __kernel_size_t unique_len; /**< Length of unique */ ++ char *unique; /**< Unique name for driver instantiation */ ++}; ++ ++struct drm_list { ++ int count; /**< Length of user-space structures */ ++ struct drm_version *version; ++}; ++ ++struct drm_block { ++ int unused; ++}; ++ +/* -+ * 2 plane YCbCr -+ * index 0 = Y plane, [39:0] Y3:Y2:Y1:Y0 little endian -+ * index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian ++ * DRM_IOCTL_CONTROL ioctl argument type. ++ * ++ * \sa drmCtlInstHandler() and drmCtlUninstHandler(). + */ -+#define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */ ++struct drm_control { ++ enum { ++ DRM_ADD_COMMAND, ++ DRM_RM_COMMAND, ++ DRM_INST_HANDLER, ++ DRM_UNINST_HANDLER ++ } func; ++ int irq; ++}; + +/* -+ * 2 plane YCbCr MSB aligned -+ * index 0 = Y plane, [15:0] Y:x [10:6] little endian -+ * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian ++ * Type of memory to map. + */ -+#define DRM_FORMAT_P210 fourcc_code('P', '2', '1', '0') /* 2x1 subsampled Cr:Cb plane, 10 bit per channel */ ++enum drm_map_type { ++ _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */ ++ _DRM_REGISTERS = 1, /**< no caching, no core dump */ ++ _DRM_SHM = 2, /**< shared, cached */ ++ _DRM_AGP = 3, /**< AGP/GART */ ++ _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */ ++ _DRM_CONSISTENT = 5 /**< Consistent memory for PCI DMA */ ++}; + +/* -+ * 2 plane YCbCr MSB aligned -+ * index 0 = Y plane, [15:0] Y:x [10:6] little endian -+ * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian ++ * Memory mapping flags. + */ -+#define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */ ++enum drm_map_flags { ++ _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */ ++ _DRM_READ_ONLY = 0x02, ++ _DRM_LOCKED = 0x04, /**< shared, cached, locked */ ++ _DRM_KERNEL = 0x08, /**< kernel requires access */ ++ _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */ ++ _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */ ++ _DRM_REMOVABLE = 0x40, /**< Removable mapping */ ++ _DRM_DRIVER = 0x80 /**< Managed by driver */ ++}; ++ ++struct drm_ctx_priv_map { ++ unsigned int ctx_id; /**< Context requesting private mapping */ ++ void *handle; /**< Handle of map */ ++}; + +/* -+ * 2 plane YCbCr MSB aligned -+ * index 0 = Y plane, [15:0] Y:x [12:4] little endian -+ * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian ++ * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls ++ * argument type. ++ * ++ * \sa drmAddMap(). + */ -+#define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */ ++struct drm_map { ++ unsigned long offset; /**< Requested physical address (0 for SAREA)*/ ++ unsigned long size; /**< Requested physical size (bytes) */ ++ enum drm_map_type type; /**< Type of memory to map */ ++ enum drm_map_flags flags; /**< Flags */ ++ void *handle; /**< User-space: "Handle" to pass to mmap() */ ++ /**< Kernel-space: kernel-virtual address */ ++ int mtrr; /**< MTRR slot used */ ++ /* Private data */ ++}; + +/* -+ * 2 plane YCbCr MSB aligned -+ * index 0 = Y plane, [15:0] Y little endian -+ * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian ++ * DRM_IOCTL_GET_CLIENT ioctl argument type. + */ -+#define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */ ++struct drm_client { ++ int idx; /**< Which client desired? */ ++ int auth; /**< Is client authenticated? */ ++ unsigned long pid; /**< Process ID */ ++ unsigned long uid; /**< User ID */ ++ unsigned long magic; /**< Magic */ ++ unsigned long iocs; /**< Ioctl count */ ++}; + -+/* 3 plane non-subsampled (444) YCbCr -+ * 16 bits per component, but only 10 bits are used and 6 bits are padded -+ * index 0: Y plane, [15:0] Y:x [10:6] little endian -+ * index 1: Cb plane, [15:0] Cb:x [10:6] little endian -+ * index 2: Cr plane, [15:0] Cr:x [10:6] little endian ++enum drm_stat_type { ++ _DRM_STAT_LOCK, ++ _DRM_STAT_OPENS, ++ _DRM_STAT_CLOSES, ++ _DRM_STAT_IOCTLS, ++ _DRM_STAT_LOCKS, ++ _DRM_STAT_UNLOCKS, ++ _DRM_STAT_VALUE, /**< Generic value */ ++ _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */ ++ _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */ ++ ++ _DRM_STAT_IRQ, /**< IRQ */ ++ _DRM_STAT_PRIMARY, /**< Primary DMA bytes */ ++ _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */ ++ _DRM_STAT_DMA, /**< DMA */ ++ _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */ ++ _DRM_STAT_MISSED /**< Missed DMA opportunity */ ++ /* Add to the *END* of the list */ ++}; ++ ++/* ++ * DRM_IOCTL_GET_STATS ioctl argument type. + */ -+#define DRM_FORMAT_Q410 fourcc_code('Q', '4', '1', '0') ++struct drm_stats { ++ unsigned long count; ++ struct { ++ unsigned long value; ++ enum drm_stat_type type; ++ } data[15]; ++}; + -+/* 3 plane non-subsampled (444) YCrCb -+ * 16 bits per component, but only 10 bits are used and 6 bits are padded -+ * index 0: Y plane, [15:0] Y:x [10:6] little endian -+ * index 1: Cr plane, [15:0] Cr:x [10:6] little endian -+ * index 2: Cb plane, [15:0] Cb:x [10:6] little endian ++/* ++ * Hardware locking flags. + */ -+#define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1') ++enum drm_lock_flags { ++ _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */ ++ _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */ ++ _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */ ++ _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */ ++ /* These *HALT* flags aren't supported yet ++ -- they will be used to support the ++ full-screen DGA-like mode. */ ++ _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */ ++ _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */ ++}; + +/* -+ * 3 plane YCbCr -+ * index 0: Y plane, [7:0] Y -+ * index 1: Cb plane, [7:0] Cb -+ * index 2: Cr plane, [7:0] Cr -+ * or -+ * index 1: Cr plane, [7:0] Cr -+ * index 2: Cb plane, [7:0] Cb ++ * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type. ++ * ++ * \sa drmGetLock() and drmUnlock(). + */ -+#define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */ -+#define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */ -+#define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */ -+#define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */ -+#define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */ -+#define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */ -+#define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */ -+#define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */ -+#define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */ -+#define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */ -+ ++struct drm_lock { ++ int context; ++ enum drm_lock_flags flags; ++}; + +/* -+ * Format Modifiers: ++ * DMA flags + * -+ * Format modifiers describe, typically, a re-ordering or modification -+ * of the data in a plane of an FB. This can be used to express tiled/ -+ * swizzled formats, or compression, or a combination of the two. ++ * \warning ++ * These values \e must match xf86drm.h. + * -+ * The upper 8 bits of the format modifier are a vendor-id as assigned -+ * below. The lower 56 bits are assigned as vendor sees fit. ++ * \sa drm_dma. + */ ++enum drm_dma_flags { ++ /* Flags for DMA buffer dispatch */ ++ _DRM_DMA_BLOCK = 0x01, /**< ++ * Block until buffer dispatched. ++ * ++ * \note The buffer may not yet have ++ * been processed by the hardware -- ++ * getting a hardware lock with the ++ * hardware quiescent will ensure ++ * that the buffer has been ++ * processed. ++ */ ++ _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */ ++ _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */ + -+/* Vendor Ids: */ -+#define DRM_FORMAT_MOD_VENDOR_NONE 0 -+#define DRM_FORMAT_MOD_VENDOR_INTEL 0x01 -+#define DRM_FORMAT_MOD_VENDOR_AMD 0x02 -+#define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03 -+#define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04 -+#define DRM_FORMAT_MOD_VENDOR_QCOM 0x05 -+#define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06 -+#define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07 -+#define DRM_FORMAT_MOD_VENDOR_ARM 0x08 -+#define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09 -+#define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a -+ -+/* add more to the end as needed */ -+ -+#define DRM_FORMAT_RESERVED ((1ULL << 56) - 1) -+ -+#define fourcc_mod_get_vendor(modifier) \ -+ (((modifier) >> 56) & 0xff) -+ -+#define fourcc_mod_is_vendor(modifier, vendor) \ -+ (fourcc_mod_get_vendor(modifier) == DRM_FORMAT_MOD_VENDOR_## vendor) -+ -+#define fourcc_mod_code(vendor, val) \ -+ ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL)) ++ /* Flags for DMA buffer request */ ++ _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */ ++ _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */ ++ _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */ ++}; + +/* -+ * Format Modifier tokens: -+ * -+ * When adding a new token please document the layout with a code comment, -+ * similar to the fourcc codes above. drm_fourcc.h is considered the -+ * authoritative source for all of these. -+ * -+ * Generic modifier names: -+ * -+ * DRM_FORMAT_MOD_GENERIC_* definitions are used to provide vendor-neutral names -+ * for layouts which are common across multiple vendors. To preserve -+ * compatibility, in cases where a vendor-specific definition already exists and -+ * a generic name for it is desired, the common name is a purely symbolic alias -+ * and must use the same numerical value as the original definition. -+ * -+ * Note that generic names should only be used for modifiers which describe -+ * generic layouts (such as pixel re-ordering), which may have -+ * independently-developed support across multiple vendors. -+ * -+ * In future cases where a generic layout is identified before merging with a -+ * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor -+ * 'NONE' could be considered. This should only be for obvious, exceptional -+ * cases to avoid polluting the 'GENERIC' namespace with modifiers which only -+ * apply to a single vendor. ++ * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type. + * -+ * Generic names should not be used for cases where multiple hardware vendors -+ * have implementations of the same standardised compression scheme (such as -+ * AFBC). In those cases, all implementations should use the same format -+ * modifier(s), reflecting the vendor of the standard. ++ * \sa drmAddBufs(). + */ -+ -+#define DRM_FORMAT_MOD_GENERIC_16_16_TILE DRM_FORMAT_MOD_SAMSUNG_16_16_TILE ++struct drm_buf_desc { ++ int count; /**< Number of buffers of this size */ ++ int size; /**< Size in bytes */ ++ int low_mark; /**< Low water mark */ ++ int high_mark; /**< High water mark */ ++ enum { ++ _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */ ++ _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */ ++ _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */ ++ _DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */ ++ _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */ ++ } flags; ++ unsigned long agp_start; /**< ++ * Start address of where the AGP buffers are ++ * in the AGP aperture ++ */ ++}; + +/* -+ * Invalid Modifier -+ * -+ * This modifier can be used as a sentinel to terminate the format modifiers -+ * list, or to initialize a variable with an invalid modifier. It might also be -+ * used to report an error back to userspace for certain APIs. ++ * DRM_IOCTL_INFO_BUFS ioctl argument type. + */ -+#define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED) ++struct drm_buf_info { ++ int count; /**< Entries in list */ ++ struct drm_buf_desc *list; ++}; + +/* -+ * Linear Layout -+ * -+ * Just plain linear layout. Note that this is different from no specifying any -+ * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl), -+ * which tells the driver to also take driver-internal information into account -+ * and so might actually result in a tiled framebuffer. ++ * DRM_IOCTL_FREE_BUFS ioctl argument type. + */ -+#define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0) ++struct drm_buf_free { ++ int count; ++ int *list; ++}; + +/* -+ * Deprecated: use DRM_FORMAT_MOD_LINEAR instead ++ * Buffer information + * -+ * The "none" format modifier doesn't actually mean that the modifier is -+ * implicit, instead it means that the layout is linear. Whether modifiers are -+ * used is out-of-band information carried in an API-specific way (e.g. in a -+ * flag for drm_mode_fb_cmd2). ++ * \sa drm_buf_map. + */ -+#define DRM_FORMAT_MOD_NONE 0 ++struct drm_buf_pub { ++ int idx; /**< Index into the master buffer list */ ++ int total; /**< Buffer size */ ++ int used; /**< Amount of buffer in use (for DMA) */ ++ void *address; /**< Address of buffer */ ++}; + -+/* Intel framebuffer modifiers */ ++/* ++ * DRM_IOCTL_MAP_BUFS ioctl argument type. ++ */ ++struct drm_buf_map { ++ int count; /**< Length of the buffer list */ ++#ifdef __cplusplus ++ void *virt; ++#else ++ void *virtual; /**< Mmap'd area in user-virtual */ ++#endif ++ struct drm_buf_pub *list; /**< Buffer information */ ++}; + +/* -+ * Intel X-tiling layout ++ * DRM_IOCTL_DMA ioctl argument type. + * -+ * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) -+ * in row-major layout. Within the tile bytes are laid out row-major, with -+ * a platform-dependent stride. On top of that the memory can apply -+ * platform-depending swizzling of some higher address bits into bit6. ++ * Indices here refer to the offset into the buffer list in drm_buf_get. + * -+ * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets. -+ * On earlier platforms the is highly platforms specific and not useful for -+ * cross-driver sharing. It exists since on a given platform it does uniquely -+ * identify the layout in a simple way for i915-specific userspace, which -+ * facilitated conversion of userspace to modifiers. Additionally the exact -+ * format on some really old platforms is not known. ++ * \sa drmDMA(). + */ -+#define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1) ++struct drm_dma { ++ int context; /**< Context handle */ ++ int send_count; /**< Number of buffers to send */ ++ int *send_indices; /**< List of handles to buffers */ ++ int *send_sizes; /**< Lengths of data to send */ ++ enum drm_dma_flags flags; /**< Flags */ ++ int request_count; /**< Number of buffers requested */ ++ int request_size; /**< Desired size for buffers */ ++ int *request_indices; /**< Buffer information */ ++ int *request_sizes; ++ int granted_count; /**< Number of buffers granted */ ++}; ++ ++enum drm_ctx_flags { ++ _DRM_CONTEXT_PRESERVED = 0x01, ++ _DRM_CONTEXT_2DONLY = 0x02 ++}; + +/* -+ * Intel Y-tiling layout -+ * -+ * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) -+ * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes) -+ * chunks column-major, with a platform-dependent height. On top of that the -+ * memory can apply platform-depending swizzling of some higher address bits -+ * into bit6. ++ * DRM_IOCTL_ADD_CTX ioctl argument type. + * -+ * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets. -+ * On earlier platforms the is highly platforms specific and not useful for -+ * cross-driver sharing. It exists since on a given platform it does uniquely -+ * identify the layout in a simple way for i915-specific userspace, which -+ * facilitated conversion of userspace to modifiers. Additionally the exact -+ * format on some really old platforms is not known. ++ * \sa drmCreateContext() and drmDestroyContext(). ++ */ ++struct drm_ctx { ++ drm_context_t handle; ++ enum drm_ctx_flags flags; ++}; ++ ++/* ++ * DRM_IOCTL_RES_CTX ioctl argument type. + */ -+#define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2) ++struct drm_ctx_res { ++ int count; ++ struct drm_ctx *contexts; ++}; + +/* -+ * Intel Yf-tiling layout -+ * -+ * This is a tiled layout using 4Kb tiles in row-major layout. -+ * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which -+ * are arranged in four groups (two wide, two high) with column-major layout. -+ * Each group therefore consits out of four 256 byte units, which are also laid -+ * out as 2x2 column-major. -+ * 256 byte units are made out of four 64 byte blocks of pixels, producing -+ * either a square block or a 2:1 unit. -+ * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width -+ * in pixel depends on the pixel depth. ++ * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type. + */ -+#define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3) ++struct drm_draw { ++ drm_drawable_t handle; ++}; + +/* -+ * Intel color control surface (CCS) for render compression -+ * -+ * The framebuffer format must be one of the 8:8:8:8 RGB formats. -+ * The main surface will be plane index 0 and must be Y/Yf-tiled, -+ * the CCS will be plane index 1. -+ * -+ * Each CCS tile matches a 1024x512 pixel area of the main surface. -+ * To match certain aspects of the 3D hardware the CCS is -+ * considered to be made up of normal 128Bx32 Y tiles, Thus -+ * the CCS pitch must be specified in multiples of 128 bytes. -+ * -+ * In reality the CCS tile appears to be a 64Bx64 Y tile, composed -+ * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks. -+ * But that fact is not relevant unless the memory is accessed -+ * directly. ++ * DRM_IOCTL_UPDATE_DRAW ioctl argument type. + */ -+#define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4) -+#define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5) ++typedef enum { ++ DRM_DRAWABLE_CLIPRECTS ++} drm_drawable_info_type_t; ++ ++struct drm_update_draw { ++ drm_drawable_t handle; ++ unsigned int type; ++ unsigned int num; ++ unsigned long long data; ++}; + +/* -+ * Intel color control surfaces (CCS) for Gen-12 render compression. -+ * -+ * The main surface is Y-tiled and at plane index 0, the CCS is linear and -+ * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in -+ * main surface. In other words, 4 bits in CCS map to a main surface cache -+ * line pair. The main surface pitch is required to be a multiple of four -+ * Y-tile widths. ++ * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type. + */ -+#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6) ++struct drm_auth { ++ drm_magic_t magic; ++}; + +/* -+ * Intel color control surfaces (CCS) for Gen-12 media compression ++ * DRM_IOCTL_IRQ_BUSID ioctl argument type. + * -+ * The main surface is Y-tiled and at plane index 0, the CCS is linear and -+ * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in -+ * main surface. In other words, 4 bits in CCS map to a main surface cache -+ * line pair. The main surface pitch is required to be a multiple of four -+ * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the -+ * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces, -+ * planes 2 and 3 for the respective CCS. ++ * \sa drmGetInterruptFromBusID(). + */ -+#define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7) ++struct drm_irq_busid { ++ int irq; /**< IRQ number */ ++ int busnum; /**< bus number */ ++ int devnum; /**< device number */ ++ int funcnum; /**< function number */ ++}; ++ ++enum drm_vblank_seq_type { ++ _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */ ++ _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */ ++ /* bits 1-6 are reserved for high crtcs */ ++ _DRM_VBLANK_HIGH_CRTC_MASK = 0x0000003e, ++ _DRM_VBLANK_EVENT = 0x4000000, /**< Send event instead of blocking */ ++ _DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */ ++ _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */ ++ _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */ ++ _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking, unsupported */ ++}; ++#define _DRM_VBLANK_HIGH_CRTC_SHIFT 1 ++ ++#define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE) ++#define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT | _DRM_VBLANK_SIGNAL | \ ++ _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS) ++ ++struct drm_wait_vblank_request { ++ enum drm_vblank_seq_type type; ++ unsigned int sequence; ++ unsigned long signal; ++}; ++ ++struct drm_wait_vblank_reply { ++ enum drm_vblank_seq_type type; ++ unsigned int sequence; ++ long tval_sec; ++ long tval_usec; ++}; + +/* -+ * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render -+ * compression. ++ * DRM_IOCTL_WAIT_VBLANK ioctl argument type. + * -+ * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear -+ * and at index 1. The clear color is stored at index 2, and the pitch should -+ * be ignored. The clear color structure is 256 bits. The first 128 bits -+ * represents Raw Clear Color Red, Green, Blue and Alpha color each represented -+ * by 32 bits. The raw clear color is consumed by the 3d engine and generates -+ * the converted clear color of size 64 bits. The first 32 bits store the Lower -+ * Converted Clear Color value and the next 32 bits store the Higher Converted -+ * Clear Color value when applicable. The Converted Clear Color values are -+ * consumed by the DE. The last 64 bits are used to store Color Discard Enable -+ * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line -+ * corresponds to an area of 4x1 tiles in the main surface. The main surface -+ * pitch is required to be a multiple of 4 tile widths. ++ * \sa drmWaitVBlank(). + */ -+#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8) ++union drm_wait_vblank { ++ struct drm_wait_vblank_request request; ++ struct drm_wait_vblank_reply reply; ++}; ++ ++#define _DRM_PRE_MODESET 1 ++#define _DRM_POST_MODESET 2 + +/* -+ * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks -+ * -+ * Macroblocks are laid in a Z-shape, and each pixel data is following the -+ * standard NV12 style. -+ * As for NV12, an image is the result of two frame buffers: one for Y, -+ * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer). -+ * Alignment requirements are (for each buffer): -+ * - multiple of 128 pixels for the width -+ * - multiple of 32 pixels for the height ++ * DRM_IOCTL_MODESET_CTL ioctl argument type + * -+ * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html ++ * \sa drmModesetCtl(). + */ -+#define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1) ++struct drm_modeset_ctl { ++ __u32 crtc; ++ __u32 cmd; ++}; + +/* -+ * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks ++ * DRM_IOCTL_AGP_ENABLE ioctl argument type. + * -+ * This is a simple tiled layout using tiles of 16x16 pixels in a row-major -+ * layout. For YCbCr formats Cb/Cr components are taken in such a way that -+ * they correspond to their 16x16 luma block. ++ * \sa drmAgpEnable(). + */ -+#define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE fourcc_mod_code(SAMSUNG, 2) ++struct drm_agp_mode { ++ unsigned long mode; /**< AGP mode */ ++}; + +/* -+ * Qualcomm Compressed Format -+ * -+ * Refers to a compressed variant of the base format that is compressed. -+ * Implementation may be platform and base-format specific. ++ * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type. + * -+ * Each macrotile consists of m x n (mostly 4 x 4) tiles. -+ * Pixel data pitch/stride is aligned with macrotile width. -+ * Pixel data height is aligned with macrotile height. -+ * Entire pixel data buffer is aligned with 4k(bytes). ++ * \sa drmAgpAlloc() and drmAgpFree(). + */ -+#define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1) -+ -+/* Vivante framebuffer modifiers */ ++struct drm_agp_buffer { ++ unsigned long size; /**< In bytes -- will round to page boundary */ ++ unsigned long handle; /**< Used for binding / unbinding */ ++ unsigned long type; /**< Type of memory to allocate */ ++ unsigned long physical; /**< Physical used by i810 */ ++}; + +/* -+ * Vivante 4x4 tiling layout ++ * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type. + * -+ * This is a simple tiled layout using tiles of 4x4 pixels in a row-major -+ * layout. ++ * \sa drmAgpBind() and drmAgpUnbind(). + */ -+#define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1) ++struct drm_agp_binding { ++ unsigned long handle; /**< From drm_agp_buffer */ ++ unsigned long offset; /**< In bytes -- will round to page boundary */ ++}; + +/* -+ * Vivante 64x64 super-tiling layout -+ * -+ * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile -+ * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row- -+ * major layout. ++ * DRM_IOCTL_AGP_INFO ioctl argument type. + * -+ * For more information: see -+ * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling ++ * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(), ++ * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(), ++ * drmAgpVendorId() and drmAgpDeviceId(). + */ -+#define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2) ++struct drm_agp_info { ++ int agp_version_major; ++ int agp_version_minor; ++ unsigned long mode; ++ unsigned long aperture_base; /* physical address */ ++ unsigned long aperture_size; /* bytes */ ++ unsigned long memory_allowed; /* bytes */ ++ unsigned long memory_used; ++ ++ /* PCI information */ ++ unsigned short id_vendor; ++ unsigned short id_device; ++}; + +/* -+ * Vivante 4x4 tiling layout for dual-pipe -+ * -+ * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a -+ * different base address. Offsets from the base addresses are therefore halved -+ * compared to the non-split tiled layout. ++ * DRM_IOCTL_SG_ALLOC ioctl argument type. + */ -+#define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3) ++struct drm_scatter_gather { ++ unsigned long size; /**< In bytes -- will round to page boundary */ ++ unsigned long handle; /**< Used for mapping / unmapping */ ++}; + +/* -+ * Vivante 64x64 super-tiling layout for dual-pipe -+ * -+ * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile -+ * starts at a different base address. Offsets from the base addresses are -+ * therefore halved compared to the non-split super-tiled layout. ++ * DRM_IOCTL_SET_VERSION ioctl argument type. + */ -+#define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4) ++struct drm_set_version { ++ int drm_di_major; ++ int drm_di_minor; ++ int drm_dd_major; ++ int drm_dd_minor; ++}; ++ ++/* DRM_IOCTL_GEM_CLOSE ioctl argument type */ ++struct drm_gem_close { ++ /** Handle of the object to be closed. */ ++ __u32 handle; ++ __u32 pad; ++}; ++ ++/* DRM_IOCTL_GEM_FLINK ioctl argument type */ ++struct drm_gem_flink { ++ /** Handle for the object being named */ ++ __u32 handle; ++ ++ /** Returned global name */ ++ __u32 name; ++}; + -+/* NVIDIA frame buffer modifiers */ ++/* DRM_IOCTL_GEM_OPEN ioctl argument type */ ++struct drm_gem_open { ++ /** Name of object being opened */ ++ __u32 name; + -+/* -+ * Tegra Tiled Layout, used by Tegra 2, 3 and 4. -+ * -+ * Pixels are arranged in simple tiles of 16 x 16 bytes. -+ */ -+#define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1) ++ /** Returned handle for the object */ ++ __u32 handle; + -+/* -+ * Generalized Block Linear layout, used by desktop GPUs starting with NV50/G80, -+ * and Tegra GPUs starting with Tegra K1. -+ * -+ * Pixels are arranged in Groups of Bytes (GOBs). GOB size and layout varies -+ * based on the architecture generation. GOBs themselves are then arranged in -+ * 3D blocks, with the block dimensions (in terms of GOBs) always being a power -+ * of two, and hence expressible as their log2 equivalent (E.g., "2" represents -+ * a block depth or height of "4"). -+ * -+ * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format -+ * in full detail. -+ * -+ * Macro -+ * Bits Param Description -+ * ---- ----- ----------------------------------------------------------------- -+ * -+ * 3:0 h log2(height) of each block, in GOBs. Placed here for -+ * compatibility with the existing -+ * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers. ++ /** Returned size of the object */ ++ __u64 size; ++}; ++ ++/** ++ * DRM_CAP_DUMB_BUFFER + * -+ * 4:4 - Must be 1, to indicate block-linear layout. Necessary for -+ * compatibility with the existing -+ * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers. ++ * If set to 1, the driver supports creating dumb buffers via the ++ * &DRM_IOCTL_MODE_CREATE_DUMB ioctl. ++ */ ++#define DRM_CAP_DUMB_BUFFER 0x1 ++/** ++ * DRM_CAP_VBLANK_HIGH_CRTC + * -+ * 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block -+ * size). Must be zero. ++ * If set to 1, the kernel supports specifying a :ref:`CRTC index` ++ * in the high bits of &drm_wait_vblank_request.type. + * -+ * Note there is no log2(width) parameter. Some portions of the -+ * hardware support a block width of two gobs, but it is impractical -+ * to use due to lack of support elsewhere, and has no known -+ * benefits. ++ * Starting kernel version 2.6.39, this capability is always set to 1. ++ */ ++#define DRM_CAP_VBLANK_HIGH_CRTC 0x2 ++/** ++ * DRM_CAP_DUMB_PREFERRED_DEPTH + * -+ * 11:9 - Reserved (To support 2D-array textures with variable array stride -+ * in blocks, specified via log2(tile width in blocks)). Must be -+ * zero. ++ * The preferred bit depth for dumb buffers. + * -+ * 19:12 k Page Kind. This value directly maps to a field in the page -+ * tables of all GPUs >= NV50. It affects the exact layout of bits -+ * in memory and can be derived from the tuple ++ * The bit depth is the number of bits used to indicate the color of a single ++ * pixel excluding any padding. This is different from the number of bits per ++ * pixel. For instance, XRGB8888 has a bit depth of 24 but has 32 bits per ++ * pixel. + * -+ * (format, GPU model, compression type, samples per pixel) ++ * Note that this preference only applies to dumb buffers, it's irrelevant for ++ * other types of buffers. ++ */ ++#define DRM_CAP_DUMB_PREFERRED_DEPTH 0x3 ++/** ++ * DRM_CAP_DUMB_PREFER_SHADOW + * -+ * Where compression type is defined below. If GPU model were -+ * implied by the format modifier, format, or memory buffer, page -+ * kind would not need to be included in the modifier itself, but -+ * since the modifier should define the layout of the associated -+ * memory buffer independent from any device or other context, it -+ * must be included here. ++ * If set to 1, the driver prefers userspace to render to a shadow buffer ++ * instead of directly rendering to a dumb buffer. For best speed, userspace ++ * should do streaming ordered memory copies into the dumb buffer and never ++ * read from it. + * -+ * 21:20 g GOB Height and Page Kind Generation. The height of a GOB changed -+ * starting with Fermi GPUs. Additionally, the mapping between page -+ * kind and bit layout has changed at various points. ++ * Note that this preference only applies to dumb buffers, it's irrelevant for ++ * other types of buffers. ++ */ ++#define DRM_CAP_DUMB_PREFER_SHADOW 0x4 ++/** ++ * DRM_CAP_PRIME + * -+ * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping -+ * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping -+ * 2 = Gob Height 8, Turing+ Page Kind mapping -+ * 3 = Reserved for future use. ++ * Bitfield of supported PRIME sharing capabilities. See &DRM_PRIME_CAP_IMPORT ++ * and &DRM_PRIME_CAP_EXPORT. + * -+ * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further -+ * bit remapping step that occurs at an even lower level than the -+ * page kind and block linear swizzles. This causes the layout of -+ * surfaces mapped in those SOC's GPUs to be incompatible with the -+ * equivalent mapping on other GPUs in the same system. ++ * PRIME buffers are exposed as dma-buf file descriptors. See ++ * Documentation/gpu/drm-mm.rst, section "PRIME Buffer Sharing". ++ */ ++#define DRM_CAP_PRIME 0x5 ++/** ++ * DRM_PRIME_CAP_IMPORT + * -+ * 0 = Tegra K1 - Tegra Parker/TX2 Layout. -+ * 1 = Desktop GPU and Tegra Xavier+ Layout ++ * If this bit is set in &DRM_CAP_PRIME, the driver supports importing PRIME ++ * buffers via the &DRM_IOCTL_PRIME_FD_TO_HANDLE ioctl. ++ */ ++#define DRM_PRIME_CAP_IMPORT 0x1 ++/** ++ * DRM_PRIME_CAP_EXPORT + * -+ * 25:23 c Lossless Framebuffer Compression type. ++ * If this bit is set in &DRM_CAP_PRIME, the driver supports exporting PRIME ++ * buffers via the &DRM_IOCTL_PRIME_HANDLE_TO_FD ioctl. ++ */ ++#define DRM_PRIME_CAP_EXPORT 0x2 ++/** ++ * DRM_CAP_TIMESTAMP_MONOTONIC + * -+ * 0 = none -+ * 1 = ROP/3D, layout 1, exact compression format implied by Page -+ * Kind field -+ * 2 = ROP/3D, layout 2, exact compression format implied by Page -+ * Kind field -+ * 3 = CDE horizontal -+ * 4 = CDE vertical -+ * 5 = Reserved for future use -+ * 6 = Reserved for future use -+ * 7 = Reserved for future use ++ * If set to 0, the kernel will report timestamps with ``CLOCK_REALTIME`` in ++ * struct drm_event_vblank. If set to 1, the kernel will report timestamps with ++ * ``CLOCK_MONOTONIC``. See ``clock_gettime(2)`` for the definition of these ++ * clocks. + * -+ * 55:25 - Reserved for future use. Must be zero. -+ */ -+#define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \ -+ fourcc_mod_code(NVIDIA, (0x10 | \ -+ ((h) & 0xf) | \ -+ (((k) & 0xff) << 12) | \ -+ (((g) & 0x3) << 20) | \ -+ (((s) & 0x1) << 22) | \ -+ (((c) & 0x7) << 23))) -+ -+/* To grandfather in prior block linear format modifiers to the above layout, -+ * the page kind "0", which corresponds to "pitch/linear" and hence is unusable -+ * with block-linear layouts, is remapped within drivers to the value 0xfe, -+ * which corresponds to the "generic" kind used for simple single-sample -+ * uncompressed color formats on Fermi - Volta GPUs. ++ * Starting from kernel version 2.6.39, the default value for this capability ++ * is 1. Starting kernel version 4.15, this capability is always set to 1. + */ -+static __inline__ __u64 -+drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) -+{ -+ if (!(modifier & 0x10) || (modifier & (0xff << 12))) -+ return modifier; -+ else -+ return modifier | (0xfe << 12); -+} -+ -+/* -+ * 16Bx2 Block Linear layout, used by Tegra K1 and later -+ * -+ * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked -+ * vertically by a power of 2 (1 to 32 GOBs) to form a block. ++#define DRM_CAP_TIMESTAMP_MONOTONIC 0x6 ++/** ++ * DRM_CAP_ASYNC_PAGE_FLIP + * -+ * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape. ++ * If set to 1, the driver supports &DRM_MODE_PAGE_FLIP_ASYNC. ++ */ ++#define DRM_CAP_ASYNC_PAGE_FLIP 0x7 ++/** ++ * DRM_CAP_CURSOR_WIDTH + * -+ * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically. -+ * Valid values are: ++ * The ``CURSOR_WIDTH`` and ``CURSOR_HEIGHT`` capabilities return a valid ++ * width x height combination for the hardware cursor. The intention is that a ++ * hardware agnostic userspace can query a cursor plane size to use. + * -+ * 0 == ONE_GOB -+ * 1 == TWO_GOBS -+ * 2 == FOUR_GOBS -+ * 3 == EIGHT_GOBS -+ * 4 == SIXTEEN_GOBS -+ * 5 == THIRTYTWO_GOBS ++ * Note that the cross-driver contract is to merely return a valid size; ++ * drivers are free to attach another meaning on top, eg. i915 returns the ++ * maximum plane size. ++ */ ++#define DRM_CAP_CURSOR_WIDTH 0x8 ++/** ++ * DRM_CAP_CURSOR_HEIGHT + * -+ * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format -+ * in full detail. ++ * See &DRM_CAP_CURSOR_WIDTH. + */ -+#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \ -+ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 0, 0, 0, (v)) -+ -+#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \ -+ DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0) -+#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \ -+ DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1) -+#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \ -+ DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2) -+#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \ -+ DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3) -+#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \ -+ DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4) -+#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \ -+ DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5) -+ -+/* -+ * Some Broadcom modifiers take parameters, for example the number of -+ * vertical lines in the image. Reserve the lower 32 bits for modifier -+ * type, and the next 24 bits for parameters. Top 8 bits are the -+ * vendor code. ++#define DRM_CAP_CURSOR_HEIGHT 0x9 ++/** ++ * DRM_CAP_ADDFB2_MODIFIERS ++ * ++ * If set to 1, the driver supports supplying modifiers in the ++ * &DRM_IOCTL_MODE_ADDFB2 ioctl. + */ -+#define __fourcc_mod_broadcom_param_shift 8 -+#define __fourcc_mod_broadcom_param_bits 48 -+#define fourcc_mod_broadcom_code(val, params) \ -+ fourcc_mod_code(BROADCOM, ((((__u64)params) << __fourcc_mod_broadcom_param_shift) | val)) -+#define fourcc_mod_broadcom_param(m) \ -+ ((int)(((m) >> __fourcc_mod_broadcom_param_shift) & \ -+ ((1ULL << __fourcc_mod_broadcom_param_bits) - 1))) -+#define fourcc_mod_broadcom_mod(m) \ -+ ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \ -+ __fourcc_mod_broadcom_param_shift)) -+ -+/* -+ * Broadcom VC4 "T" format ++#define DRM_CAP_ADDFB2_MODIFIERS 0x10 ++/** ++ * DRM_CAP_PAGE_FLIP_TARGET + * -+ * This is the primary layout that the V3D GPU can texture from (it -+ * can't do linear). The T format has: ++ * If set to 1, the driver supports the &DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE and ++ * &DRM_MODE_PAGE_FLIP_TARGET_RELATIVE flags in ++ * &drm_mode_crtc_page_flip_target.flags for the &DRM_IOCTL_MODE_PAGE_FLIP ++ * ioctl. ++ */ ++#define DRM_CAP_PAGE_FLIP_TARGET 0x11 ++/** ++ * DRM_CAP_CRTC_IN_VBLANK_EVENT + * -+ * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4 -+ * pixels at 32 bit depth. ++ * If set to 1, the kernel supports reporting the CRTC ID in ++ * &drm_event_vblank.crtc_id for the &DRM_EVENT_VBLANK and ++ * &DRM_EVENT_FLIP_COMPLETE events. + * -+ * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually -+ * 16x16 pixels). ++ * Starting kernel version 4.12, this capability is always set to 1. ++ */ ++#define DRM_CAP_CRTC_IN_VBLANK_EVENT 0x12 ++/** ++ * DRM_CAP_SYNCOBJ + * -+ * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On -+ * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows -+ * they're (TR, BR, BL, TL), where bottom left is start of memory. ++ * If set to 1, the driver supports sync objects. See ++ * Documentation/gpu/drm-mm.rst, section "DRM Sync Objects". ++ */ ++#define DRM_CAP_SYNCOBJ 0x13 ++/** ++ * DRM_CAP_SYNCOBJ_TIMELINE + * -+ * - an image made of 4k tiles in rows either left-to-right (even rows of 4k -+ * tiles) or right-to-left (odd rows of 4k tiles). ++ * If set to 1, the driver supports timeline operations on sync objects. See ++ * Documentation/gpu/drm-mm.rst, section "DRM Sync Objects". + */ -+#define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1) ++#define DRM_CAP_SYNCOBJ_TIMELINE 0x14 + -+/* -+ * Broadcom SAND format ++/* DRM_IOCTL_GET_CAP ioctl argument type */ ++struct drm_get_cap { ++ __u64 capability; ++ __u64 value; ++}; ++ ++/** ++ * DRM_CLIENT_CAP_STEREO_3D + * -+ * This is the native format that the H.264 codec block uses. For VC4 -+ * HVS, it is only valid for H.264 (NV12/21) and RGBA modes. ++ * If set to 1, the DRM core will expose the stereo 3D capabilities of the ++ * monitor by advertising the supported 3D layouts in the flags of struct ++ * drm_mode_modeinfo. See ``DRM_MODE_FLAG_3D_*``. + * -+ * The image can be considered to be split into columns, and the -+ * columns are placed consecutively into memory. The width of those -+ * columns can be either 32, 64, 128, or 256 pixels, but in practice -+ * only 128 pixel columns are used. ++ * This capability is always supported for all drivers starting from kernel ++ * version 3.13. ++ */ ++#define DRM_CLIENT_CAP_STEREO_3D 1 ++ ++/** ++ * DRM_CLIENT_CAP_UNIVERSAL_PLANES + * -+ * The pitch between the start of each column is set to optimally -+ * switch between SDRAM banks. This is passed as the number of lines -+ * of column width in the modifier (we can't use the stride value due -+ * to various core checks that look at it , so you should set the -+ * stride to width*cpp). ++ * If set to 1, the DRM core will expose all planes (overlay, primary, and ++ * cursor) to userspace. + * -+ * Note that the column height for this format modifier is the same -+ * for all of the planes, assuming that each column contains both Y -+ * and UV. Some SAND-using hardware stores UV in a separate tiled -+ * image from Y to reduce the column height, which is not supported -+ * with these modifiers. ++ * This capability has been introduced in kernel version 3.15. Starting from ++ * kernel version 3.17, this capability is always supported for all drivers. + */ ++#define DRM_CLIENT_CAP_UNIVERSAL_PLANES 2 + -+#define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \ -+ fourcc_mod_broadcom_code(2, v) -+#define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \ -+ fourcc_mod_broadcom_code(3, v) -+#define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \ -+ fourcc_mod_broadcom_code(4, v) -+#define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \ -+ fourcc_mod_broadcom_code(5, v) -+ -+#define DRM_FORMAT_MOD_BROADCOM_SAND32 \ -+ DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0) -+#define DRM_FORMAT_MOD_BROADCOM_SAND64 \ -+ DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0) -+#define DRM_FORMAT_MOD_BROADCOM_SAND128 \ -+ DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0) -+#define DRM_FORMAT_MOD_BROADCOM_SAND256 \ -+ DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0) -+ -+/* Broadcom UIF format ++/** ++ * DRM_CLIENT_CAP_ATOMIC + * -+ * This is the common format for the current Broadcom multimedia -+ * blocks, including V3D 3.x and newer, newer video codecs, and -+ * displays. ++ * If set to 1, the DRM core will expose atomic properties to userspace. This ++ * implicitly enables &DRM_CLIENT_CAP_UNIVERSAL_PLANES and ++ * &DRM_CLIENT_CAP_ASPECT_RATIO. + * -+ * The image consists of utiles (64b blocks), UIF blocks (2x2 utiles), -+ * and macroblocks (4x4 UIF blocks). Those 4x4 UIF block groups are -+ * stored in columns, with padding between the columns to ensure that -+ * moving from one column to the next doesn't hit the same SDRAM page -+ * bank. ++ * If the driver doesn't support atomic mode-setting, enabling this capability ++ * will fail with -EOPNOTSUPP. + * -+ * To calculate the padding, it is assumed that each hardware block -+ * and the software driving it knows the platform's SDRAM page size, -+ * number of banks, and XOR address, and that it's identical between -+ * all blocks using the format. This tiling modifier will use XOR as -+ * necessary to reduce the padding. If a hardware block can't do XOR, -+ * the assumption is that a no-XOR tiling modifier will be created. ++ * This capability has been introduced in kernel version 4.0. Starting from ++ * kernel version 4.2, this capability is always supported for atomic-capable ++ * drivers. + */ -+#define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6) ++#define DRM_CLIENT_CAP_ATOMIC 3 + -+/* -+ * Arm Framebuffer Compression (AFBC) modifiers -+ * -+ * AFBC is a proprietary lossless image compression protocol and format. -+ * It provides fine-grained random access and minimizes the amount of data -+ * transferred between IP blocks. ++/** ++ * DRM_CLIENT_CAP_ASPECT_RATIO + * -+ * AFBC has several features which may be supported and/or used, which are -+ * represented using bits in the modifier. Not all combinations are valid, -+ * and different devices or use-cases may support different combinations. ++ * If set to 1, the DRM core will provide aspect ratio information in modes. ++ * See ``DRM_MODE_FLAG_PIC_AR_*``. + * -+ * Further information on the use of AFBC modifiers can be found in -+ * Documentation/gpu/afbc.rst ++ * This capability is always supported for all drivers starting from kernel ++ * version 4.18. + */ ++#define DRM_CLIENT_CAP_ASPECT_RATIO 4 + -+/* -+ * The top 4 bits (out of the 56 bits alloted for specifying vendor specific -+ * modifiers) denote the category for modifiers. Currently we have three -+ * categories of modifiers ie AFBC, MISC and AFRC. We can have a maximum of -+ * sixteen different categories. ++/** ++ * DRM_CLIENT_CAP_WRITEBACK_CONNECTORS ++ * ++ * If set to 1, the DRM core will expose special connectors to be used for ++ * writing back to memory the scene setup in the commit. The client must enable ++ * &DRM_CLIENT_CAP_ATOMIC first. ++ * ++ * This capability is always supported for atomic-capable drivers starting from ++ * kernel version 4.19. + */ -+#define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \ -+ fourcc_mod_code(ARM, ((__u64)(__type) << 52) | ((__val) & 0x000fffffffffffffULL)) ++#define DRM_CLIENT_CAP_WRITEBACK_CONNECTORS 5 + -+#define DRM_FORMAT_MOD_ARM_TYPE_AFBC 0x00 -+#define DRM_FORMAT_MOD_ARM_TYPE_MISC 0x01 ++/* DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */ ++struct drm_set_client_cap { ++ __u64 capability; ++ __u64 value; ++}; + -+#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) \ -+ DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode) ++#define DRM_RDWR O_RDWR ++#define DRM_CLOEXEC O_CLOEXEC ++struct drm_prime_handle { ++ __u32 handle; + -+/* -+ * AFBC superblock size -+ * -+ * Indicates the superblock size(s) used for the AFBC buffer. The buffer -+ * size (in pixels) must be aligned to a multiple of the superblock size. -+ * Four lowest significant bits(LSBs) are reserved for block size. -+ * -+ * Where one superblock size is specified, it applies to all planes of the -+ * buffer (e.g. 16x16, 32x8). When multiple superblock sizes are specified, -+ * the first applies to the Luma plane and the second applies to the Chroma -+ * plane(s). e.g. (32x8_64x4 means 32x8 Luma, with 64x4 Chroma). -+ * Multiple superblock sizes are only valid for multi-plane YCbCr formats. -+ */ -+#define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf -+#define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL) -+#define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL) -+#define AFBC_FORMAT_MOD_BLOCK_SIZE_64x4 (3ULL) -+#define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL) ++ /** Flags.. only applicable for handle->fd */ ++ __u32 flags; + -+/* -+ * AFBC lossless colorspace transform -+ * -+ * Indicates that the buffer makes use of the AFBC lossless colorspace -+ * transform. -+ */ -+#define AFBC_FORMAT_MOD_YTR (1ULL << 4) ++ /** Returned dmabuf file descriptor */ ++ __s32 fd; ++}; ++ ++struct drm_syncobj_create { ++ __u32 handle; ++#define DRM_SYNCOBJ_CREATE_SIGNALED (1 << 0) ++ __u32 flags; ++}; ++ ++struct drm_syncobj_destroy { ++ __u32 handle; ++ __u32 pad; ++}; ++ ++#define DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_IMPORT_SYNC_FILE (1 << 0) ++#define DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_SYNC_FILE (1 << 0) ++struct drm_syncobj_handle { ++ __u32 handle; ++ __u32 flags; ++ ++ __s32 fd; ++ __u32 pad; ++}; ++ ++struct drm_syncobj_transfer { ++ __u32 src_handle; ++ __u32 dst_handle; ++ __u64 src_point; ++ __u64 dst_point; ++ __u32 flags; ++ __u32 pad; ++}; ++ ++#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL (1 << 0) ++#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT (1 << 1) ++#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABLE (1 << 2) /* wait for time point to become available */ ++struct drm_syncobj_wait { ++ __u64 handles; ++ /* absolute timeout */ ++ __s64 timeout_nsec; ++ __u32 count_handles; ++ __u32 flags; ++ __u32 first_signaled; /* only valid when not waiting all */ ++ __u32 pad; ++}; ++ ++struct drm_syncobj_timeline_wait { ++ __u64 handles; ++ /* wait on specific timeline point for every handles*/ ++ __u64 points; ++ /* absolute timeout */ ++ __s64 timeout_nsec; ++ __u32 count_handles; ++ __u32 flags; ++ __u32 first_signaled; /* only valid when not waiting all */ ++ __u32 pad; ++}; + -+/* -+ * AFBC block-split -+ * -+ * Indicates that the payload of each superblock is split. The second -+ * half of the payload is positioned at a predefined offset from the start -+ * of the superblock payload. -+ */ -+#define AFBC_FORMAT_MOD_SPLIT (1ULL << 5) + -+/* -+ * AFBC sparse layout -+ * -+ * This flag indicates that the payload of each superblock must be stored at a -+ * predefined position relative to the other superblocks in the same AFBC -+ * buffer. This order is the same order used by the header buffer. In this mode -+ * each superblock is given the same amount of space as an uncompressed -+ * superblock of the particular format would require, rounding up to the next -+ * multiple of 128 bytes in size. -+ */ -+#define AFBC_FORMAT_MOD_SPARSE (1ULL << 6) ++struct drm_syncobj_array { ++ __u64 handles; ++ __u32 count_handles; ++ __u32 pad; ++}; + -+/* -+ * AFBC copy-block restrict -+ * -+ * Buffers with this flag must obey the copy-block restriction. The restriction -+ * is such that there are no copy-blocks referring across the border of 8x8 -+ * blocks. For the subsampled data the 8x8 limitation is also subsampled. -+ */ -+#define AFBC_FORMAT_MOD_CBR (1ULL << 7) ++#define DRM_SYNCOBJ_QUERY_FLAGS_LAST_SUBMITTED (1 << 0) /* last available point on timeline syncobj */ ++struct drm_syncobj_timeline_array { ++ __u64 handles; ++ __u64 points; ++ __u32 count_handles; ++ __u32 flags; ++}; + -+/* -+ * AFBC tiled layout -+ * -+ * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all -+ * superblocks inside a tile are stored together in memory. 8x8 tiles are used -+ * for pixel formats up to and including 32 bpp while 4x4 tiles are used for -+ * larger bpp formats. The order between the tiles is scan line. -+ * When the tiled layout is used, the buffer size (in pixels) must be aligned -+ * to the tile size. -+ */ -+#define AFBC_FORMAT_MOD_TILED (1ULL << 8) + -+/* -+ * AFBC solid color blocks -+ * -+ * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth -+ * can be reduced if a whole superblock is a single color. -+ */ -+#define AFBC_FORMAT_MOD_SC (1ULL << 9) ++/* Query current scanout sequence number */ ++struct drm_crtc_get_sequence { ++ __u32 crtc_id; /* requested crtc_id */ ++ __u32 active; /* return: crtc output is active */ ++ __u64 sequence; /* return: most recent vblank sequence */ ++ __s64 sequence_ns; /* return: most recent time of first pixel out */ ++}; + -+/* -+ * AFBC double-buffer -+ * -+ * Indicates that the buffer is allocated in a layout safe for front-buffer -+ * rendering. ++/* Queue event to be delivered at specified sequence. Time stamp marks ++ * when the first pixel of the refresh cycle leaves the display engine ++ * for the display + */ -+#define AFBC_FORMAT_MOD_DB (1ULL << 10) ++#define DRM_CRTC_SEQUENCE_RELATIVE 0x00000001 /* sequence is relative to current */ ++#define DRM_CRTC_SEQUENCE_NEXT_ON_MISS 0x00000002 /* Use next sequence if we've missed */ + -+/* -+ * AFBC buffer content hints -+ * -+ * Indicates that the buffer includes per-superblock content hints. -+ */ -+#define AFBC_FORMAT_MOD_BCH (1ULL << 11) ++struct drm_crtc_queue_sequence { ++ __u32 crtc_id; ++ __u32 flags; ++ __u64 sequence; /* on input, target sequence. on output, actual sequence */ ++ __u64 user_data; /* user data passed to event */ ++}; + -+/* AFBC uncompressed storage mode -+ * -+ * Indicates that the buffer is using AFBC uncompressed storage mode. -+ * In this mode all superblock payloads in the buffer use the uncompressed -+ * storage mode, which is usually only used for data which cannot be compressed. -+ * The buffer layout is the same as for AFBC buffers without USM set, this only -+ * affects the storage mode of the individual superblocks. Note that even a -+ * buffer without USM set may use uncompressed storage mode for some or all -+ * superblocks, USM just guarantees it for all. -+ */ -+#define AFBC_FORMAT_MOD_USM (1ULL << 12) ++#if defined(__cplusplus) ++} ++#endif + -+/* -+ * Arm Fixed-Rate Compression (AFRC) modifiers -+ * -+ * AFRC is a proprietary fixed rate image compression protocol and format, -+ * designed to provide guaranteed bandwidth and memory footprint -+ * reductions in graphics and media use-cases. -+ * -+ * AFRC buffers consist of one or more planes, with the same components -+ * and meaning as an uncompressed buffer using the same pixel format. -+ * -+ * Within each plane, the pixel/luma/chroma values are grouped into -+ * "coding unit" blocks which are individually compressed to a -+ * fixed size (in bytes). All coding units within a given plane of a buffer -+ * store the same number of values, and have the same compressed size. -+ * -+ * The coding unit size is configurable, allowing different rates of compression. -+ * -+ * The start of each AFRC buffer plane must be aligned to an alignment granule which -+ * depends on the coding unit size. -+ * -+ * Coding Unit Size Plane Alignment -+ * ---------------- --------------- -+ * 16 bytes 1024 bytes -+ * 24 bytes 512 bytes -+ * 32 bytes 2048 bytes -+ * -+ * Coding units are grouped into paging tiles. AFRC buffer dimensions must be aligned -+ * to a multiple of the paging tile dimensions. -+ * The dimensions of each paging tile depend on whether the buffer is optimised for -+ * scanline (SCAN layout) or rotated (ROT layout) access. -+ * -+ * Layout Paging Tile Width Paging Tile Height -+ * ------ ----------------- ------------------ -+ * SCAN 16 coding units 4 coding units -+ * ROT 8 coding units 8 coding units -+ * -+ * The dimensions of each coding unit depend on the number of components -+ * in the compressed plane and whether the buffer is optimised for -+ * scanline (SCAN layout) or rotated (ROT layout) access. -+ * -+ * Number of Components in Plane Layout Coding Unit Width Coding Unit Height -+ * ----------------------------- --------- ----------------- ------------------ -+ * 1 SCAN 16 samples 4 samples -+ * Example: 16x4 luma samples in a 'Y' plane -+ * 16x4 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer -+ * ----------------------------- --------- ----------------- ------------------ -+ * 1 ROT 8 samples 8 samples -+ * Example: 8x8 luma samples in a 'Y' plane -+ * 8x8 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer -+ * ----------------------------- --------- ----------------- ------------------ -+ * 2 DONT CARE 8 samples 4 samples -+ * Example: 8x4 chroma pairs in the 'UV' plane of a semi-planar YUV buffer -+ * ----------------------------- --------- ----------------- ------------------ -+ * 3 DONT CARE 4 samples 4 samples -+ * Example: 4x4 pixels in an RGB buffer without alpha -+ * ----------------------------- --------- ----------------- ------------------ -+ * 4 DONT CARE 4 samples 4 samples -+ * Example: 4x4 pixels in an RGB buffer with alpha -+ */ ++#include "drm_mode.h" + -+#define DRM_FORMAT_MOD_ARM_TYPE_AFRC 0x02 ++#if defined(__cplusplus) ++extern "C" { ++#endif + -+#define DRM_FORMAT_MOD_ARM_AFRC(__afrc_mode) \ -+ DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFRC, __afrc_mode) ++#define DRM_IOCTL_BASE 'd' ++#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr) ++#define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type) ++#define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type) ++#define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type) + -+/* -+ * AFRC coding unit size modifier. -+ * -+ * Indicates the number of bytes used to store each compressed coding unit for -+ * one or more planes in an AFRC encoded buffer. The coding unit size for chrominance -+ * is the same for both Cb and Cr, which may be stored in separate planes. -+ * -+ * AFRC_FORMAT_MOD_CU_SIZE_P0 indicates the number of bytes used to store -+ * each compressed coding unit in the first plane of the buffer. For RGBA buffers -+ * this is the only plane, while for semi-planar and fully-planar YUV buffers, -+ * this corresponds to the luma plane. -+ * -+ * AFRC_FORMAT_MOD_CU_SIZE_P12 indicates the number of bytes used to store -+ * each compressed coding unit in the second and third planes in the buffer. -+ * For semi-planar and fully-planar YUV buffers, this corresponds to the chroma plane(s). -+ * -+ * For single-plane buffers, AFRC_FORMAT_MOD_CU_SIZE_P0 must be specified -+ * and AFRC_FORMAT_MOD_CU_SIZE_P12 must be zero. -+ * For semi-planar and fully-planar buffers, both AFRC_FORMAT_MOD_CU_SIZE_P0 and -+ * AFRC_FORMAT_MOD_CU_SIZE_P12 must be specified. -+ */ -+#define AFRC_FORMAT_MOD_CU_SIZE_MASK 0xf -+#define AFRC_FORMAT_MOD_CU_SIZE_16 (1ULL) -+#define AFRC_FORMAT_MOD_CU_SIZE_24 (2ULL) -+#define AFRC_FORMAT_MOD_CU_SIZE_32 (3ULL) ++#define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version) ++#define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, struct drm_unique) ++#define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, struct drm_auth) ++#define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, struct drm_irq_busid) ++#define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map) ++#define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client) ++#define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats) ++#define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version) ++#define DRM_IOCTL_MODESET_CTL DRM_IOW(0x08, struct drm_modeset_ctl) ++#define DRM_IOCTL_GEM_CLOSE DRM_IOW (0x09, struct drm_gem_close) ++#define DRM_IOCTL_GEM_FLINK DRM_IOWR(0x0a, struct drm_gem_flink) ++#define DRM_IOCTL_GEM_OPEN DRM_IOWR(0x0b, struct drm_gem_open) ++#define DRM_IOCTL_GET_CAP DRM_IOWR(0x0c, struct drm_get_cap) ++#define DRM_IOCTL_SET_CLIENT_CAP DRM_IOW( 0x0d, struct drm_set_client_cap) + -+#define AFRC_FORMAT_MOD_CU_SIZE_P0(__afrc_cu_size) (__afrc_cu_size) -+#define AFRC_FORMAT_MOD_CU_SIZE_P12(__afrc_cu_size) ((__afrc_cu_size) << 4) ++#define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique) ++#define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth) ++#define DRM_IOCTL_BLOCK DRM_IOWR(0x12, struct drm_block) ++#define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, struct drm_block) ++#define DRM_IOCTL_CONTROL DRM_IOW( 0x14, struct drm_control) ++#define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map) ++#define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, struct drm_buf_desc) ++#define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, struct drm_buf_desc) ++#define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info) ++#define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, struct drm_buf_map) ++#define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, struct drm_buf_free) + -+/* -+ * AFRC scanline memory layout. -+ * -+ * Indicates if the buffer uses the scanline-optimised layout -+ * for an AFRC encoded buffer, otherwise, it uses the rotation-optimised layout. -+ * The memory layout is the same for all planes. -+ */ -+#define AFRC_FORMAT_MOD_LAYOUT_SCAN (1ULL << 8) ++#define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map) + -+/* -+ * Arm 16x16 Block U-Interleaved modifier -+ * -+ * This is used by Arm Mali Utgard and Midgard GPUs. It divides the image -+ * into 16x16 pixel blocks. Blocks are stored linearly in order, but pixels -+ * in the block are reordered. -+ */ -+#define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED \ -+ DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL) ++#define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map) ++#define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map) + -+/* -+ * Allwinner tiled modifier -+ * -+ * This tiling mode is implemented by the VPU found on all Allwinner platforms, -+ * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3 -+ * planes. -+ * -+ * With this tiling, the luminance samples are disposed in tiles representing -+ * 32x32 pixels and the chrominance samples in tiles representing 32x64 pixels. -+ * The pixel order in each tile is linear and the tiles are disposed linearly, -+ * both in row-major order. -+ */ -+#define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1) ++#define DRM_IOCTL_SET_MASTER DRM_IO(0x1e) ++#define DRM_IOCTL_DROP_MASTER DRM_IO(0x1f) ++ ++#define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx) ++#define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx) ++#define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, struct drm_ctx) ++#define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, struct drm_ctx) ++#define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, struct drm_ctx) ++#define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, struct drm_ctx) ++#define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, struct drm_ctx_res) ++#define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, struct drm_draw) ++#define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, struct drm_draw) ++#define DRM_IOCTL_DMA DRM_IOWR(0x29, struct drm_dma) ++#define DRM_IOCTL_LOCK DRM_IOW( 0x2a, struct drm_lock) ++#define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock) ++#define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock) + -+/* -+ * Amlogic Video Framebuffer Compression modifiers -+ * -+ * Amlogic uses a proprietary lossless image compression protocol and format -+ * for their hardware video codec accelerators, either video decoders or -+ * video input encoders. -+ * -+ * It considerably reduces memory bandwidth while writing and reading -+ * frames in memory. -+ * -+ * The underlying storage is considered to be 3 components, 8bit or 10-bit -+ * per component YCbCr 420, single plane : -+ * - DRM_FORMAT_YUV420_8BIT -+ * - DRM_FORMAT_YUV420_10BIT -+ * -+ * The first 8 bits of the mode defines the layout, then the following 8 bits -+ * defines the options changing the layout. -+ * -+ * Not all combinations are valid, and different SoCs may support different -+ * combinations of layout and options. -+ */ -+#define __fourcc_mod_amlogic_layout_mask 0xff -+#define __fourcc_mod_amlogic_options_shift 8 -+#define __fourcc_mod_amlogic_options_mask 0xff ++#define DRM_IOCTL_PRIME_HANDLE_TO_FD DRM_IOWR(0x2d, struct drm_prime_handle) ++#define DRM_IOCTL_PRIME_FD_TO_HANDLE DRM_IOWR(0x2e, struct drm_prime_handle) + -+#define DRM_FORMAT_MOD_AMLOGIC_FBC(__layout, __options) \ -+ fourcc_mod_code(AMLOGIC, \ -+ ((__layout) & __fourcc_mod_amlogic_layout_mask) | \ -+ (((__options) & __fourcc_mod_amlogic_options_mask) \ -+ << __fourcc_mod_amlogic_options_shift)) ++#define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30) ++#define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31) ++#define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, struct drm_agp_mode) ++#define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, struct drm_agp_info) ++#define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, struct drm_agp_buffer) ++#define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, struct drm_agp_buffer) ++#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding) ++#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding) + -+/* Amlogic FBC Layouts */ ++#define DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather) ++#define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather) + -+/* -+ * Amlogic FBC Basic Layout -+ * -+ * The basic layout is composed of: -+ * - a body content organized in 64x32 superblocks with 4096 bytes per -+ * superblock in default mode. -+ * - a 32 bytes per 128x64 header block -+ * -+ * This layout is transferrable between Amlogic SoCs supporting this modifier. -+ */ -+#define AMLOGIC_FBC_LAYOUT_BASIC (1ULL) ++#define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank) + -+/* -+ * Amlogic FBC Scatter Memory layout -+ * -+ * Indicates the header contains IOMMU references to the compressed -+ * frames content to optimize memory access and layout. -+ * -+ * In this mode, only the header memory address is needed, thus the -+ * content memory organization is tied to the current producer -+ * execution and cannot be saved/dumped neither transferrable between -+ * Amlogic SoCs supporting this modifier. -+ * -+ * Due to the nature of the layout, these buffers are not expected to -+ * be accessible by the user-space clients, but only accessible by the -+ * hardware producers and consumers. -+ * -+ * The user-space clients should expect a failure while trying to mmap -+ * the DMA-BUF handle returned by the producer. -+ */ -+#define AMLOGIC_FBC_LAYOUT_SCATTER (2ULL) ++#define DRM_IOCTL_CRTC_GET_SEQUENCE DRM_IOWR(0x3b, struct drm_crtc_get_sequence) ++#define DRM_IOCTL_CRTC_QUEUE_SEQUENCE DRM_IOWR(0x3c, struct drm_crtc_queue_sequence) + -+/* Amlogic FBC Layout Options Bit Mask */ ++#define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw) + -+/* -+ * Amlogic FBC Memory Saving mode -+ * -+ * Indicates the storage is packed when pixel size is multiple of word -+ * boudaries, i.e. 8bit should be stored in this mode to save allocation -+ * memory. -+ * -+ * This mode reduces body layout to 3072 bytes per 64x32 superblock with -+ * the basic layout and 3200 bytes per 64x32 superblock combined with -+ * the scatter layout. -+ */ -+#define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0) ++#define DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res) ++#define DRM_IOCTL_MODE_GETCRTC DRM_IOWR(0xA1, struct drm_mode_crtc) ++#define DRM_IOCTL_MODE_SETCRTC DRM_IOWR(0xA2, struct drm_mode_crtc) ++#define DRM_IOCTL_MODE_CURSOR DRM_IOWR(0xA3, struct drm_mode_cursor) ++#define DRM_IOCTL_MODE_GETGAMMA DRM_IOWR(0xA4, struct drm_mode_crtc_lut) ++#define DRM_IOCTL_MODE_SETGAMMA DRM_IOWR(0xA5, struct drm_mode_crtc_lut) ++#define DRM_IOCTL_MODE_GETENCODER DRM_IOWR(0xA6, struct drm_mode_get_encoder) ++#define DRM_IOCTL_MODE_GETCONNECTOR DRM_IOWR(0xA7, struct drm_mode_get_connector) ++#define DRM_IOCTL_MODE_ATTACHMODE DRM_IOWR(0xA8, struct drm_mode_mode_cmd) /* deprecated (never worked) */ ++#define DRM_IOCTL_MODE_DETACHMODE DRM_IOWR(0xA9, struct drm_mode_mode_cmd) /* deprecated (never worked) */ + -+/* -+ * AMD modifiers -+ * -+ * Memory layout: -+ * -+ * without DCC: -+ * - main surface -+ * -+ * with DCC & without DCC_RETILE: -+ * - main surface in plane 0 -+ * - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set) -+ * -+ * with DCC & DCC_RETILE: -+ * - main surface in plane 0 -+ * - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned) -+ * - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned) -+ * -+ * For multi-plane formats the above surfaces get merged into one plane for -+ * each format plane, based on the required alignment only. ++#define DRM_IOCTL_MODE_GETPROPERTY DRM_IOWR(0xAA, struct drm_mode_get_property) ++#define DRM_IOCTL_MODE_SETPROPERTY DRM_IOWR(0xAB, struct drm_mode_connector_set_property) ++#define DRM_IOCTL_MODE_GETPROPBLOB DRM_IOWR(0xAC, struct drm_mode_get_blob) ++#define DRM_IOCTL_MODE_GETFB DRM_IOWR(0xAD, struct drm_mode_fb_cmd) ++#define DRM_IOCTL_MODE_ADDFB DRM_IOWR(0xAE, struct drm_mode_fb_cmd) ++/** ++ * DRM_IOCTL_MODE_RMFB - Remove a framebuffer. + * -+ * Bits Parameter Notes -+ * ----- ------------------------ --------------------------------------------- ++ * This removes a framebuffer previously added via ADDFB/ADDFB2. The IOCTL ++ * argument is a framebuffer object ID. + * -+ * 7:0 TILE_VERSION Values are AMD_FMT_MOD_TILE_VER_* -+ * 12:8 TILE Values are AMD_FMT_MOD_TILE__* -+ * 13 DCC -+ * 14 DCC_RETILE -+ * 15 DCC_PIPE_ALIGN -+ * 16 DCC_INDEPENDENT_64B -+ * 17 DCC_INDEPENDENT_128B -+ * 19:18 DCC_MAX_COMPRESSED_BLOCK Values are AMD_FMT_MOD_DCC_BLOCK_* -+ * 20 DCC_CONSTANT_ENCODE -+ * 23:21 PIPE_XOR_BITS Only for some chips -+ * 26:24 BANK_XOR_BITS Only for some chips -+ * 29:27 PACKERS Only for some chips -+ * 32:30 RB Only for some chips -+ * 35:33 PIPE Only for some chips -+ * 55:36 - Reserved for future use, must be zero ++ * Warning: removing a framebuffer currently in-use on an enabled plane will ++ * disable that plane. The CRTC the plane is linked to may also be disabled ++ * (depending on driver capabilities). + */ -+#define AMD_FMT_MOD fourcc_mod_code(AMD, 0) -+ -+#define IS_AMD_FMT_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_AMD) -+ -+/* Reserve 0 for GFX8 and older */ -+#define AMD_FMT_MOD_TILE_VER_GFX9 1 -+#define AMD_FMT_MOD_TILE_VER_GFX10 2 -+#define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3 ++#define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xAF, unsigned int) ++#define DRM_IOCTL_MODE_PAGE_FLIP DRM_IOWR(0xB0, struct drm_mode_crtc_page_flip) ++#define DRM_IOCTL_MODE_DIRTYFB DRM_IOWR(0xB1, struct drm_mode_fb_dirty_cmd) + -+/* -+ * 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical -+ * version. -+ */ -+#define AMD_FMT_MOD_TILE_GFX9_64K_S 9 ++#define DRM_IOCTL_MODE_CREATE_DUMB DRM_IOWR(0xB2, struct drm_mode_create_dumb) ++#define DRM_IOCTL_MODE_MAP_DUMB DRM_IOWR(0xB3, struct drm_mode_map_dumb) ++#define DRM_IOCTL_MODE_DESTROY_DUMB DRM_IOWR(0xB4, struct drm_mode_destroy_dumb) ++#define DRM_IOCTL_MODE_GETPLANERESOURCES DRM_IOWR(0xB5, struct drm_mode_get_plane_res) ++#define DRM_IOCTL_MODE_GETPLANE DRM_IOWR(0xB6, struct drm_mode_get_plane) ++#define DRM_IOCTL_MODE_SETPLANE DRM_IOWR(0xB7, struct drm_mode_set_plane) ++#define DRM_IOCTL_MODE_ADDFB2 DRM_IOWR(0xB8, struct drm_mode_fb_cmd2) ++#define DRM_IOCTL_MODE_OBJ_GETPROPERTIES DRM_IOWR(0xB9, struct drm_mode_obj_get_properties) ++#define DRM_IOCTL_MODE_OBJ_SETPROPERTY DRM_IOWR(0xBA, struct drm_mode_obj_set_property) ++#define DRM_IOCTL_MODE_CURSOR2 DRM_IOWR(0xBB, struct drm_mode_cursor2) ++#define DRM_IOCTL_MODE_ATOMIC DRM_IOWR(0xBC, struct drm_mode_atomic) ++#define DRM_IOCTL_MODE_CREATEPROPBLOB DRM_IOWR(0xBD, struct drm_mode_create_blob) ++#define DRM_IOCTL_MODE_DESTROYPROPBLOB DRM_IOWR(0xBE, struct drm_mode_destroy_blob) + -+/* -+ * 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has -+ * GFX9 as canonical version. -+ */ -+#define AMD_FMT_MOD_TILE_GFX9_64K_D 10 -+#define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25 -+#define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26 -+#define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27 ++#define DRM_IOCTL_SYNCOBJ_CREATE DRM_IOWR(0xBF, struct drm_syncobj_create) ++#define DRM_IOCTL_SYNCOBJ_DESTROY DRM_IOWR(0xC0, struct drm_syncobj_destroy) ++#define DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD DRM_IOWR(0xC1, struct drm_syncobj_handle) ++#define DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE DRM_IOWR(0xC2, struct drm_syncobj_handle) ++#define DRM_IOCTL_SYNCOBJ_WAIT DRM_IOWR(0xC3, struct drm_syncobj_wait) ++#define DRM_IOCTL_SYNCOBJ_RESET DRM_IOWR(0xC4, struct drm_syncobj_array) ++#define DRM_IOCTL_SYNCOBJ_SIGNAL DRM_IOWR(0xC5, struct drm_syncobj_array) + -+#define AMD_FMT_MOD_DCC_BLOCK_64B 0 -+#define AMD_FMT_MOD_DCC_BLOCK_128B 1 -+#define AMD_FMT_MOD_DCC_BLOCK_256B 2 ++#define DRM_IOCTL_MODE_CREATE_LEASE DRM_IOWR(0xC6, struct drm_mode_create_lease) ++#define DRM_IOCTL_MODE_LIST_LESSEES DRM_IOWR(0xC7, struct drm_mode_list_lessees) ++#define DRM_IOCTL_MODE_GET_LEASE DRM_IOWR(0xC8, struct drm_mode_get_lease) ++#define DRM_IOCTL_MODE_REVOKE_LEASE DRM_IOWR(0xC9, struct drm_mode_revoke_lease) + -+#define AMD_FMT_MOD_TILE_VERSION_SHIFT 0 -+#define AMD_FMT_MOD_TILE_VERSION_MASK 0xFF -+#define AMD_FMT_MOD_TILE_SHIFT 8 -+#define AMD_FMT_MOD_TILE_MASK 0x1F ++#define DRM_IOCTL_SYNCOBJ_TIMELINE_WAIT DRM_IOWR(0xCA, struct drm_syncobj_timeline_wait) ++#define DRM_IOCTL_SYNCOBJ_QUERY DRM_IOWR(0xCB, struct drm_syncobj_timeline_array) ++#define DRM_IOCTL_SYNCOBJ_TRANSFER DRM_IOWR(0xCC, struct drm_syncobj_transfer) ++#define DRM_IOCTL_SYNCOBJ_TIMELINE_SIGNAL DRM_IOWR(0xCD, struct drm_syncobj_timeline_array) + -+/* Whether DCC compression is enabled. */ -+#define AMD_FMT_MOD_DCC_SHIFT 13 -+#define AMD_FMT_MOD_DCC_MASK 0x1 ++#define DRM_IOCTL_MODE_GETFB2 DRM_IOWR(0xCE, struct drm_mode_fb_cmd2) + +/* -+ * Whether to include two DCC surfaces, one which is rb & pipe aligned, and -+ * one which is not-aligned. ++ * Device specific ioctls should only be in their respective headers ++ * The device specific ioctl range is from 0x40 to 0x9f. ++ * Generic IOCTLS restart at 0xA0. ++ * ++ * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and ++ * drmCommandReadWrite(). + */ -+#define AMD_FMT_MOD_DCC_RETILE_SHIFT 14 -+#define AMD_FMT_MOD_DCC_RETILE_MASK 0x1 -+ -+/* Only set if DCC_RETILE = false */ -+#define AMD_FMT_MOD_DCC_PIPE_ALIGN_SHIFT 15 -+#define AMD_FMT_MOD_DCC_PIPE_ALIGN_MASK 0x1 -+ -+#define AMD_FMT_MOD_DCC_INDEPENDENT_64B_SHIFT 16 -+#define AMD_FMT_MOD_DCC_INDEPENDENT_64B_MASK 0x1 -+#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17 -+#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1 -+#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18 -+#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 ++#define DRM_COMMAND_BASE 0x40 ++#define DRM_COMMAND_END 0xA0 + +/* -+ * DCC supports embedding some clear colors directly in the DCC surface. -+ * However, on older GPUs the rendering HW ignores the embedded clear color -+ * and prefers the driver provided color. This necessitates doing a fastclear -+ * eliminate operation before a process transfers control. -+ * -+ * If this bit is set that means the fastclear eliminate is not needed for these -+ * embeddable colors. ++ * Header for events written back to userspace on the drm fd. The ++ * type defines the type of event, the length specifies the total ++ * length of the event (including the header), and user_data is ++ * typically a 64 bit value passed with the ioctl that triggered the ++ * event. A read on the drm fd will always only return complete ++ * events, that is, if for example the read buffer is 100 bytes, and ++ * there are two 64 byte events pending, only one will be returned. ++ * ++ * Event types 0 - 0x7fffffff are generic drm events, 0x80000000 and ++ * up are chipset specific. + */ -+#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 20 -+#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_MASK 0x1 ++struct drm_event { ++ __u32 type; ++ __u32 length; ++}; + -+/* -+ * The below fields are for accounting for per GPU differences. These are only -+ * relevant for GFX9 and later and if the tile field is *_X/_T. -+ * -+ * PIPE_XOR_BITS = always needed -+ * BANK_XOR_BITS = only for TILE_VER_GFX9 -+ * PACKERS = only for TILE_VER_GFX10_RBPLUS -+ * RB = only for TILE_VER_GFX9 & DCC -+ * PIPE = only for TILE_VER_GFX9 & DCC & (DCC_RETILE | DCC_PIPE_ALIGN) ++#define DRM_EVENT_VBLANK 0x01 ++#define DRM_EVENT_FLIP_COMPLETE 0x02 ++#define DRM_EVENT_CRTC_SEQUENCE 0x03 ++ ++struct drm_event_vblank { ++ struct drm_event base; ++ __u64 user_data; ++ __u32 tv_sec; ++ __u32 tv_usec; ++ __u32 sequence; ++ __u32 crtc_id; /* 0 on older kernels that do not support this */ ++}; ++ ++/* Event delivered at sequence. Time stamp marks when the first pixel ++ * of the refresh cycle leaves the display engine for the display + */ -+#define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 21 -+#define AMD_FMT_MOD_PIPE_XOR_BITS_MASK 0x7 -+#define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24 -+#define AMD_FMT_MOD_BANK_XOR_BITS_MASK 0x7 -+#define AMD_FMT_MOD_PACKERS_SHIFT 27 -+#define AMD_FMT_MOD_PACKERS_MASK 0x7 -+#define AMD_FMT_MOD_RB_SHIFT 30 -+#define AMD_FMT_MOD_RB_MASK 0x7 -+#define AMD_FMT_MOD_PIPE_SHIFT 33 -+#define AMD_FMT_MOD_PIPE_MASK 0x7 ++struct drm_event_crtc_sequence { ++ struct drm_event base; ++ __u64 user_data; ++ __s64 time_ns; ++ __u64 sequence; ++}; + -+#define AMD_FMT_MOD_SET(field, value) \ -+ ((uint64_t)(value) << AMD_FMT_MOD_##field##_SHIFT) -+#define AMD_FMT_MOD_GET(field, value) \ -+ (((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK) -+#define AMD_FMT_MOD_CLEAR(field) \ -+ (~((uint64_t)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT)) ++/* typedef area */ ++typedef struct drm_clip_rect drm_clip_rect_t; ++typedef struct drm_drawable_info drm_drawable_info_t; ++typedef struct drm_tex_region drm_tex_region_t; ++typedef struct drm_hw_lock drm_hw_lock_t; ++typedef struct drm_version drm_version_t; ++typedef struct drm_unique drm_unique_t; ++typedef struct drm_list drm_list_t; ++typedef struct drm_block drm_block_t; ++typedef struct drm_control drm_control_t; ++typedef enum drm_map_type drm_map_type_t; ++typedef enum drm_map_flags drm_map_flags_t; ++typedef struct drm_ctx_priv_map drm_ctx_priv_map_t; ++typedef struct drm_map drm_map_t; ++typedef struct drm_client drm_client_t; ++typedef enum drm_stat_type drm_stat_type_t; ++typedef struct drm_stats drm_stats_t; ++typedef enum drm_lock_flags drm_lock_flags_t; ++typedef struct drm_lock drm_lock_t; ++typedef enum drm_dma_flags drm_dma_flags_t; ++typedef struct drm_buf_desc drm_buf_desc_t; ++typedef struct drm_buf_info drm_buf_info_t; ++typedef struct drm_buf_free drm_buf_free_t; ++typedef struct drm_buf_pub drm_buf_pub_t; ++typedef struct drm_buf_map drm_buf_map_t; ++typedef struct drm_dma drm_dma_t; ++typedef union drm_wait_vblank drm_wait_vblank_t; ++typedef struct drm_agp_mode drm_agp_mode_t; ++typedef enum drm_ctx_flags drm_ctx_flags_t; ++typedef struct drm_ctx drm_ctx_t; ++typedef struct drm_ctx_res drm_ctx_res_t; ++typedef struct drm_draw drm_draw_t; ++typedef struct drm_update_draw drm_update_draw_t; ++typedef struct drm_auth drm_auth_t; ++typedef struct drm_irq_busid drm_irq_busid_t; ++typedef enum drm_vblank_seq_type drm_vblank_seq_type_t; ++ ++typedef struct drm_agp_buffer drm_agp_buffer_t; ++typedef struct drm_agp_binding drm_agp_binding_t; ++typedef struct drm_agp_info drm_agp_info_t; ++typedef struct drm_scatter_gather drm_scatter_gather_t; ++typedef struct drm_set_version drm_set_version_t; + +#if defined(__cplusplus) +} +#endif + -+#endif /* DRM_FOURCC_H */ -diff --git a/third_party/drm/drm/drm_mode.h b/third_party/drm/drm/drm_mode.h -new file mode 100644 -index 0000000..e1e3516 ---- /dev/null -+++ b/third_party/drm/drm/drm_mode.h ++#endif +diff -up firefox-101.0/third_party/drm/drm/drm_mode.h.libwebrtc-screen-cast-sync firefox-101.0/third_party/drm/drm/drm_mode.h +--- firefox-101.0/third_party/drm/drm/drm_mode.h.libwebrtc-screen-cast-sync 2022-05-30 21:33:19.741522076 +0200 ++++ firefox-101.0/third_party/drm/drm/drm_mode.h 2022-05-30 21:33:19.741522076 +0200 @@ -0,0 +1,1217 @@ +/* + * Copyright (c) 2007 Dave Airlie @@ -3832,11 +3809,9 @@ index 0000000..e1e3516 +#endif + +#endif -diff --git a/third_party/drm/drm/xf86drm.h b/third_party/drm/drm/xf86drm.h -new file mode 100644 -index 0000000..58d66f1 ---- /dev/null -+++ b/third_party/drm/drm/xf86drm.h +diff -up firefox-101.0/third_party/drm/drm/xf86drm.h.libwebrtc-screen-cast-sync firefox-101.0/third_party/drm/drm/xf86drm.h +--- firefox-101.0/third_party/drm/drm/xf86drm.h.libwebrtc-screen-cast-sync 2022-05-30 21:33:19.742522110 +0200 ++++ firefox-101.0/third_party/drm/drm/xf86drm.h 2022-05-30 21:33:19.742522110 +0200 @@ -0,0 +1,966 @@ +/** + * \file xf86drm.h @@ -4804,11 +4779,9 @@ index 0000000..58d66f1 +#endif + +#endif -diff --git a/third_party/drm/libdrm/moz.build b/third_party/drm/libdrm/moz.build -new file mode 100644 -index 0000000..3b37b91 ---- /dev/null -+++ b/third_party/drm/libdrm/moz.build +diff -up firefox-101.0/third_party/drm/libdrm/moz.build.libwebrtc-screen-cast-sync firefox-101.0/third_party/drm/libdrm/moz.build +--- firefox-101.0/third_party/drm/libdrm/moz.build.libwebrtc-screen-cast-sync 2022-05-30 21:33:19.742522110 +0200 ++++ firefox-101.0/third_party/drm/libdrm/moz.build 2022-05-30 21:33:19.742522110 +0200 @@ -0,0 +1,16 @@ +# -*- Mode: python; indent-tabs-mode: nil; tab-width: 40 -*- +# vim: set filetype=python: @@ -4826,11 +4799,9 @@ index 0000000..3b37b91 +LOCAL_INCLUDES += ['/third_party/drm'] + +FINAL_LIBRARY = 'xul' -diff --git a/third_party/drm/libdrm/mozdrm.cpp b/third_party/drm/libdrm/mozdrm.cpp -new file mode 100644 -index 0000000..b2fb59b ---- /dev/null -+++ b/third_party/drm/libdrm/mozdrm.cpp +diff -up firefox-101.0/third_party/drm/libdrm/mozdrm.cpp.libwebrtc-screen-cast-sync firefox-101.0/third_party/drm/libdrm/mozdrm.cpp +--- firefox-101.0/third_party/drm/libdrm/mozdrm.cpp.libwebrtc-screen-cast-sync 2022-05-30 21:33:19.742522110 +0200 ++++ firefox-101.0/third_party/drm/libdrm/mozdrm.cpp 2022-05-30 21:33:19.742522110 +0200 @@ -0,0 +1,66 @@ +/* -*- Mode: C; tab-width: 4; indent-tabs-mode: nil; c-basic-offset: 2 -*- */ +/* vim:expandtab:shiftwidth=4:tabstop=4: @@ -4898,21 +4869,17 @@ index 0000000..b2fb59b + } + return drmFreeDevices_fn(devices, count); +} -diff --git a/third_party/gbm/README b/third_party/gbm/README -new file mode 100644 -index 0000000..4b6e2e8 ---- /dev/null -+++ b/third_party/gbm/README +diff -up firefox-101.0/third_party/drm/README.libwebrtc-screen-cast-sync firefox-101.0/third_party/drm/README +--- firefox-101.0/third_party/drm/README.libwebrtc-screen-cast-sync 2022-05-30 21:33:19.740522043 +0200 ++++ firefox-101.0/third_party/drm/README 2022-05-30 21:33:19.740522043 +0200 @@ -0,0 +1,4 @@ -+Libgbm is a gbm library wrapper needed to build and run Firefox with -+Pipewire support on Linux (https://gitlab.freedesktop.org/mesa/gbm). ++Libdrm is a drm library wrapper needed to build and run Firefox with ++Pipewire support on Linux (https://gitlab.freedesktop.org/mesa/drm). + -+libgbm directory stores headers of libgbm needed for build only. -diff --git a/third_party/gbm/gbm/gbm.h b/third_party/gbm/gbm/gbm.h -new file mode 100644 -index 0000000..a963ed7 ---- /dev/null -+++ b/third_party/gbm/gbm/gbm.h ++libdrm directory stores headers of libdrm needed for build only. +diff -up firefox-101.0/third_party/gbm/gbm/gbm.h.libwebrtc-screen-cast-sync firefox-101.0/third_party/gbm/gbm/gbm.h +--- firefox-101.0/third_party/gbm/gbm/gbm.h.libwebrtc-screen-cast-sync 2022-05-30 21:33:19.742522110 +0200 ++++ firefox-101.0/third_party/gbm/gbm/gbm.h 2022-05-30 21:33:19.742522110 +0200 @@ -0,0 +1,452 @@ +/* + * Copyright © 2011 Intel Corporation @@ -5366,11 +5333,9 @@ index 0000000..a963ed7 +#endif + +#endif -diff --git a/third_party/gbm/libgbm/moz.build b/third_party/gbm/libgbm/moz.build -new file mode 100644 -index 0000000..0953d2f ---- /dev/null -+++ b/third_party/gbm/libgbm/moz.build +diff -up firefox-101.0/third_party/gbm/libgbm/moz.build.libwebrtc-screen-cast-sync firefox-101.0/third_party/gbm/libgbm/moz.build +--- firefox-101.0/third_party/gbm/libgbm/moz.build.libwebrtc-screen-cast-sync 2022-05-30 21:33:19.742522110 +0200 ++++ firefox-101.0/third_party/gbm/libgbm/moz.build 2022-05-30 21:33:19.742522110 +0200 @@ -0,0 +1,16 @@ +# -*- Mode: python; indent-tabs-mode: nil; tab-width: 40 -*- +# vim: set filetype=python: @@ -5388,11 +5353,9 @@ index 0000000..0953d2f +LOCAL_INCLUDES += ['/third_party/gbm'] + +FINAL_LIBRARY = 'xul' -diff --git a/third_party/gbm/libgbm/mozgbm.cpp b/third_party/gbm/libgbm/mozgbm.cpp -new file mode 100644 -index 0000000..bc024a1 ---- /dev/null -+++ b/third_party/gbm/libgbm/mozgbm.cpp +diff -up firefox-101.0/third_party/gbm/libgbm/mozgbm.cpp.libwebrtc-screen-cast-sync firefox-101.0/third_party/gbm/libgbm/mozgbm.cpp +--- firefox-101.0/third_party/gbm/libgbm/mozgbm.cpp.libwebrtc-screen-cast-sync 2022-05-30 21:33:19.742522110 +0200 ++++ firefox-101.0/third_party/gbm/libgbm/mozgbm.cpp 2022-05-30 21:33:19.742522110 +0200 @@ -0,0 +1,66 @@ +/* -*- Mode: C; tab-width: 4; indent-tabs-mode: nil; c-basic-offset: 2 -*- */ +/* vim:expandtab:shiftwidth=4:tabstop=4: @@ -5460,11 +5423,18 @@ index 0000000..bc024a1 + } + return gbm_device_destroy_fn(gbm); +} -diff --git a/third_party/libwebrtc/modules/desktop_capture/desktop_capture_generic_gn/moz.build b/third_party/libwebrtc/modules/desktop_capture/desktop_capture_generic_gn/moz.build -index a5cf923..99cabbf 100644 ---- a/third_party/libwebrtc/modules/desktop_capture/desktop_capture_generic_gn/moz.build -+++ b/third_party/libwebrtc/modules/desktop_capture/desktop_capture_generic_gn/moz.build -@@ -77,6 +77,8 @@ if CONFIG["OS_TARGET"] == "Darwin": +diff -up firefox-101.0/third_party/gbm/README.libwebrtc-screen-cast-sync firefox-101.0/third_party/gbm/README +--- firefox-101.0/third_party/gbm/README.libwebrtc-screen-cast-sync 2022-05-30 21:33:19.742522110 +0200 ++++ firefox-101.0/third_party/gbm/README 2022-05-30 21:33:19.742522110 +0200 +@@ -0,0 +1,4 @@ ++Libgbm is a gbm library wrapper needed to build and run Firefox with ++Pipewire support on Linux (https://gitlab.freedesktop.org/mesa/gbm). ++ ++libgbm directory stores headers of libgbm needed for build only. +diff -up firefox-101.0/third_party/libwebrtc/modules/desktop_capture/desktop_capture_generic_gn/moz.build.libwebrtc-screen-cast-sync firefox-101.0/third_party/libwebrtc/modules/desktop_capture/desktop_capture_generic_gn/moz.build +--- firefox-101.0/third_party/libwebrtc/modules/desktop_capture/desktop_capture_generic_gn/moz.build.libwebrtc-screen-cast-sync 2022-05-27 01:17:03.000000000 +0200 ++++ firefox-101.0/third_party/libwebrtc/modules/desktop_capture/desktop_capture_generic_gn/moz.build 2022-05-30 21:33:19.742522110 +0200 +@@ -76,6 +76,8 @@ if CONFIG["OS_TARGET"] == "Darwin": LOCAL_INCLUDES += [ "/media/libyuv/libyuv/include/", "/media/libyuv/libyuv/include/", @@ -5473,7 +5443,7 @@ index a5cf923..99cabbf 100644 "/third_party/pipewire/" ] -@@ -108,7 +110,8 @@ if CONFIG["OS_TARGET"] == "Linux": +@@ -105,7 +107,8 @@ if CONFIG["OS_TARGET"] == "Linux": LOCAL_INCLUDES += [ "/media/libyuv/libyuv/include/", "/media/libyuv/libyuv/include/", @@ -5483,38 +5453,7 @@ index a5cf923..99cabbf 100644 "/third_party/pipewire/" ] -@@ -126,15 +129,18 @@ if CONFIG["OS_TARGET"] == "Linux": - ] - - SOURCES += [ -- "/third_party/libwebrtc/modules/desktop_capture/linux/base_capturer_pipewire.cc" -+ "/third_party/libwebrtc/modules/desktop_capture/linux/base_capturer_pipewire.cc", -+ "/third_party/libwebrtc/modules/desktop_capture/linux/egl_dmabuf.cc", -+ "/third_party/libwebrtc/modules/desktop_capture/linux/mouse_cursor_monitor_pipewire.cc", -+ "/third_party/libwebrtc/modules/desktop_capture/linux/scoped_glib.cc", -+ "/third_party/libwebrtc/modules/desktop_capture/linux/screencast_portal.cc", -+ "/third_party/libwebrtc/modules/desktop_capture/linux/shared_screencast_stream.cc" - ] - - UNIFIED_SOURCES += [ - "/third_party/libwebrtc/modules/desktop_capture/linux/mouse_cursor_monitor_x11.cc", -- "/third_party/libwebrtc/modules/desktop_capture/linux/screen_capturer_pipewire.cc", - "/third_party/libwebrtc/modules/desktop_capture/linux/screen_capturer_x11.cc", - "/third_party/libwebrtc/modules/desktop_capture/linux/shared_x_display.cc", -- "/third_party/libwebrtc/modules/desktop_capture/linux/window_capturer_pipewire.cc", - "/third_party/libwebrtc/modules/desktop_capture/linux/window_capturer_x11.cc", - "/third_party/libwebrtc/modules/desktop_capture/linux/window_finder_x11.cc", - "/third_party/libwebrtc/modules/desktop_capture/linux/window_list_utils.cc", -@@ -162,6 +168,8 @@ if CONFIG["OS_TARGET"] == "OpenBSD": - - LOCAL_INCLUDES += [ - "/media/libyuv/libyuv/include/", -+ "/third_party/drm/", -+ "/third_party/gbm/", - "/third_party/pipewire/" - ] - -@@ -177,15 +185,18 @@ if CONFIG["OS_TARGET"] == "OpenBSD": +@@ -156,15 +159,18 @@ if CONFIG["OS_TARGET"] == "OpenBSD": ] SOURCES += [ @@ -5536,7 +5475,7 @@ index a5cf923..99cabbf 100644 "/third_party/libwebrtc/modules/desktop_capture/linux/window_capturer_x11.cc", "/third_party/libwebrtc/modules/desktop_capture/linux/window_finder_x11.cc", "/third_party/libwebrtc/modules/desktop_capture/linux/window_list_utils.cc", -@@ -227,6 +238,7 @@ if CONFIG["OS_TARGET"] == "WINNT": +@@ -206,6 +212,7 @@ if CONFIG["OS_TARGET"] == "WINNT": LOCAL_INCLUDES += [ "/media/libyuv/libyuv/include/", "/media/libyuv/libyuv/include/", @@ -5544,10 +5483,9 @@ index a5cf923..99cabbf 100644 "/third_party/pipewire/" ] -diff --git a/third_party/libwebrtc/modules/desktop_capture/desktop_capture_options.cc b/third_party/libwebrtc/modules/desktop_capture/desktop_capture_options.cc -index c89896d..c8ef822 100644 ---- a/third_party/libwebrtc/modules/desktop_capture/desktop_capture_options.cc -+++ b/third_party/libwebrtc/modules/desktop_capture/desktop_capture_options.cc +diff -up firefox-101.0/third_party/libwebrtc/modules/desktop_capture/desktop_capture_options.cc.libwebrtc-screen-cast-sync firefox-101.0/third_party/libwebrtc/modules/desktop_capture/desktop_capture_options.cc +--- firefox-101.0/third_party/libwebrtc/modules/desktop_capture/desktop_capture_options.cc.libwebrtc-screen-cast-sync 2022-05-27 01:17:03.000000000 +0200 ++++ firefox-101.0/third_party/libwebrtc/modules/desktop_capture/desktop_capture_options.cc 2022-05-30 21:33:19.742522110 +0200 @@ -14,6 +14,9 @@ #elif defined(WEBRTC_WIN) #include "modules/desktop_capture/win/full_screen_win_application_handler.h" @@ -5558,7 +5496,7 @@ index c89896d..c8ef822 100644 namespace webrtc { -@@ -35,6 +38,9 @@ DesktopCaptureOptions DesktopCaptureOptions::CreateDefault() { +@@ -35,6 +38,9 @@ DesktopCaptureOptions DesktopCaptureOpti #if defined(WEBRTC_USE_X11) result.set_x_display(SharedXDisplay::CreateDefault()); #endif @@ -5568,10 +5506,9 @@ index c89896d..c8ef822 100644 #if defined(WEBRTC_MAC) && !defined(WEBRTC_IOS) result.set_configuration_monitor(new DesktopConfigurationMonitor()); result.set_full_screen_window_detector( -diff --git a/third_party/libwebrtc/modules/desktop_capture/desktop_capture_options.h b/third_party/libwebrtc/modules/desktop_capture/desktop_capture_options.h -index ee0dd3a..ac56c8c 100644 ---- a/third_party/libwebrtc/modules/desktop_capture/desktop_capture_options.h -+++ b/third_party/libwebrtc/modules/desktop_capture/desktop_capture_options.h +diff -up firefox-101.0/third_party/libwebrtc/modules/desktop_capture/desktop_capture_options.h.libwebrtc-screen-cast-sync firefox-101.0/third_party/libwebrtc/modules/desktop_capture/desktop_capture_options.h +--- firefox-101.0/third_party/libwebrtc/modules/desktop_capture/desktop_capture_options.h.libwebrtc-screen-cast-sync 2022-05-27 01:17:04.000000000 +0200 ++++ firefox-101.0/third_party/libwebrtc/modules/desktop_capture/desktop_capture_options.h 2022-05-30 21:33:19.743522143 +0200 @@ -17,6 +17,10 @@ #include "modules/desktop_capture/linux/shared_x_display.h" #endif @@ -5611,10 +5548,9 @@ index ee0dd3a..ac56c8c 100644 #if defined(WEBRTC_MAC) && !defined(WEBRTC_IOS) rtc::scoped_refptr configuration_monitor_; bool allow_iosurface_ = false; -diff --git a/third_party/libwebrtc/modules/desktop_capture/linux/base_capturer_pipewire.cc b/third_party/libwebrtc/modules/desktop_capture/linux/base_capturer_pipewire.cc -index 2fd3b1a..e4685fc 100644 ---- a/third_party/libwebrtc/modules/desktop_capture/linux/base_capturer_pipewire.cc -+++ b/third_party/libwebrtc/modules/desktop_capture/linux/base_capturer_pipewire.cc +diff -up firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/base_capturer_pipewire.cc.libwebrtc-screen-cast-sync firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/base_capturer_pipewire.cc +--- firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/base_capturer_pipewire.cc.libwebrtc-screen-cast-sync 2022-05-27 01:17:03.000000000 +0200 ++++ firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/base_capturer_pipewire.cc 2022-05-30 21:33:19.743522143 +0200 @@ -10,937 +10,67 @@ #include "modules/desktop_capture/linux/base_capturer_pipewire.h" @@ -5718,12 +5654,8 @@ index 2fd3b1a..e4685fc 100644 - case PW_STREAM_STATE_CONNECTING: - break; - } -+BaseCapturerPipeWire::BaseCapturerPipeWire(const DesktopCaptureOptions& options) -+ : options_(options) { -+ screencast_portal_ = std::make_unique( -+ ScreenCastPortal::CaptureSourceType::kAnyScreenContent, this); - } - +-} +- -// static -void BaseCapturerPipeWire::OnStreamParamChanged(void *data, uint32_t id, - const struct spa_pod *format) { @@ -5777,8 +5709,7 @@ index 2fd3b1a..e4685fc 100644 - - struct pw_buffer *next_buffer; - struct pw_buffer *buffer = nullptr; -+BaseCapturerPipeWire::~BaseCapturerPipeWire() {} - +- - next_buffer = pw_stream_dequeue_buffer(that->pw_stream_); - while (next_buffer) { - buffer = next_buffer; @@ -5791,23 +5722,13 @@ index 2fd3b1a..e4685fc 100644 - - if (!buffer) { - return; -+void BaseCapturerPipeWire::OnScreenCastRequestResult( -+ ScreenCastPortal::RequestResponse result, -+ uint32_t stream_node_id, -+ int fd) { -+ if (result != ScreenCastPortal::RequestResponse::kSuccess || -+ !options_.screencast_stream()->StartScreenCastStream(stream_node_id, -+ fd)) { -+ capturer_failed_ = true; -+ RTC_LOG(LS_ERROR) << "ScreenCastPortal failed: " -+ << static_cast(result); - } +- } - - that->HandleBuffer(buffer); - - pw_stream_queue_buffer(that->pw_stream_, buffer); - } - +-} +- -BaseCapturerPipeWire::BaseCapturerPipeWire(CaptureSourceType source_type) - : capture_source_type_(source_type) {} - @@ -5830,10 +5751,7 @@ index 2fd3b1a..e4685fc 100644 - - if (pw_main_loop_) { - pw_thread_loop_destroy(pw_main_loop_); -+void BaseCapturerPipeWire::OnScreenCastSessionClosed() { -+ if (!capturer_failed_) { -+ options_.screencast_stream()->StopScreenCastStream(); - } +- } - - if (start_request_signal_id_) { - g_dbus_connection_signal_unsubscribe(connection_, start_request_signal_id_); @@ -5877,7 +5795,25 @@ index 2fd3b1a..e4685fc 100644 - if (proxy_) { - g_object_unref(proxy_); - proxy_ = nullptr; -- } ++BaseCapturerPipeWire::BaseCapturerPipeWire(const DesktopCaptureOptions& options) ++ : options_(options) { ++ screencast_portal_ = std::make_unique( ++ ScreenCastPortal::CaptureSourceType::kAnyScreenContent, this); ++} ++ ++BaseCapturerPipeWire::~BaseCapturerPipeWire() {} ++ ++void BaseCapturerPipeWire::OnScreenCastRequestResult( ++ ScreenCastPortal::RequestResponse result, ++ uint32_t stream_node_id, ++ int fd) { ++ if (result != ScreenCastPortal::RequestResponse::kSuccess || ++ !options_.screencast_stream()->StartScreenCastStream(stream_node_id, ++ fd)) { ++ capturer_failed_ = true; ++ RTC_LOG(LS_ERROR) << "ScreenCastPortal failed: " ++ << static_cast(result); + } - - if (pw_fd_ != -1) { - close(pw_fd_); @@ -5980,17 +5916,20 @@ index 2fd3b1a..e4685fc 100644 - } - - return stream; --} -- + } + -static void SpaBufferUnmap(unsigned char *map, int map_size, bool IsDMABuf, int fd) { - if (map) { - if (IsDMABuf) { - SyncDmaBuf(fd, DMA_BUF_SYNC_END); - } - munmap(map, map_size); -- } --} -- ++void BaseCapturerPipeWire::OnScreenCastSessionClosed() { ++ if (!capturer_failed_) { ++ options_.screencast_stream()->StopScreenCastStream(); + } + } + -void BaseCapturerPipeWire::HandleBuffer(pw_buffer* buffer) { - spa_buffer* spaBuffer = buffer->buffer; - uint8_t *map = nullptr; @@ -6527,8 +6466,8 @@ index 2fd3b1a..e4685fc 100644 - g_object_unref(outlist); - - that->InitPipeWire(); - } - +-} +- void BaseCapturerPipeWire::Start(Callback* callback) { RTC_DCHECK(!callback_); RTC_DCHECK(callback); @@ -6580,7 +6519,7 @@ index 2fd3b1a..e4685fc 100644 } // Keep in sync with defines at browser/actors/WebRTCParent.jsm -@@ -953,31 +83,13 @@ void BaseCapturerPipeWire::CaptureFrame() { +@@ -953,31 +83,13 @@ void BaseCapturerPipeWire::CaptureFrame( #define PIPEWIRE_NAME "####_PIPEWIRE_PORTAL_####" bool BaseCapturerPipeWire::GetSourceList(SourceList* sources) { @@ -6613,10 +6552,9 @@ index 2fd3b1a..e4685fc 100644 -} - } // namespace webrtc -diff --git a/third_party/libwebrtc/modules/desktop_capture/linux/base_capturer_pipewire.h b/third_party/libwebrtc/modules/desktop_capture/linux/base_capturer_pipewire.h -index af8e20c..5db09e0 100644 ---- a/third_party/libwebrtc/modules/desktop_capture/linux/base_capturer_pipewire.h -+++ b/third_party/libwebrtc/modules/desktop_capture/linux/base_capturer_pipewire.h +diff -up firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/base_capturer_pipewire.h.libwebrtc-screen-cast-sync firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/base_capturer_pipewire.h +--- firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/base_capturer_pipewire.h.libwebrtc-screen-cast-sync 2022-05-27 01:17:03.000000000 +0200 ++++ firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/base_capturer_pipewire.h 2022-05-30 21:33:19.743522143 +0200 @@ -11,160 +11,39 @@ #ifndef MODULES_DESKTOP_CAPTURE_LINUX_BASE_CAPTURER_PIPEWIRE_H_ #define MODULES_DESKTOP_CAPTURE_LINUX_BASE_CAPTURER_PIPEWIRE_H_ @@ -6793,11 +6731,9 @@ index af8e20c..5db09e0 100644 }; } // namespace webrtc -diff --git a/third_party/libwebrtc/modules/desktop_capture/linux/drm.sigs b/third_party/libwebrtc/modules/desktop_capture/linux/drm.sigs -new file mode 100644 -index 0000000..226979f ---- /dev/null -+++ b/third_party/libwebrtc/modules/desktop_capture/linux/drm.sigs +diff -up firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/drm.sigs.libwebrtc-screen-cast-sync firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/drm.sigs +--- firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/drm.sigs.libwebrtc-screen-cast-sync 2022-05-30 21:33:19.743522143 +0200 ++++ firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/drm.sigs 2022-05-30 21:33:19.743522143 +0200 @@ -0,0 +1,11 @@ +// Copyright 2021 The WebRTC project authors. All rights reserved. +// Use of this source code is governed by a BSD-style license that can be @@ -6810,11 +6746,9 @@ index 0000000..226979f +// xf86drm.h +int drmGetDevices2(uint32_t flags, drmDevicePtr devices[], int max_devices); +void drmFreeDevices(drmDevicePtr devices[], int count); -diff --git a/third_party/libwebrtc/modules/desktop_capture/linux/egl_dmabuf.cc b/third_party/libwebrtc/modules/desktop_capture/linux/egl_dmabuf.cc -new file mode 100644 -index 0000000..de63c2a ---- /dev/null -+++ b/third_party/libwebrtc/modules/desktop_capture/linux/egl_dmabuf.cc +diff -up firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/egl_dmabuf.cc.libwebrtc-screen-cast-sync firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/egl_dmabuf.cc +--- firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/egl_dmabuf.cc.libwebrtc-screen-cast-sync 2022-05-30 21:33:19.743522143 +0200 ++++ firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/egl_dmabuf.cc 2022-05-30 21:33:19.743522143 +0200 @@ -0,0 +1,695 @@ +/* + * Copyright 2021 The WebRTC project authors. All Rights Reserved. @@ -7511,11 +7445,9 @@ index 0000000..de63c2a +} + +} // namespace webrtc -diff --git a/third_party/libwebrtc/modules/desktop_capture/linux/egl_dmabuf.h b/third_party/libwebrtc/modules/desktop_capture/linux/egl_dmabuf.h -new file mode 100644 -index 0000000..b755d8b ---- /dev/null -+++ b/third_party/libwebrtc/modules/desktop_capture/linux/egl_dmabuf.h +diff -up firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/egl_dmabuf.h.libwebrtc-screen-cast-sync firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/egl_dmabuf.h +--- firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/egl_dmabuf.h.libwebrtc-screen-cast-sync 2022-05-30 21:33:19.743522143 +0200 ++++ firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/egl_dmabuf.h 2022-05-30 21:33:19.743522143 +0200 @@ -0,0 +1,68 @@ +/* + * Copyright 2021 The WebRTC project authors. All Rights Reserved. @@ -7585,11 +7517,9 @@ index 0000000..b755d8b +} // namespace webrtc + +#endif // MODULES_DESKTOP_CAPTURE_LINUX_EGL_DMABUF_H_ -diff --git a/third_party/libwebrtc/modules/desktop_capture/linux/mouse_cursor_monitor_pipewire.cc b/third_party/libwebrtc/modules/desktop_capture/linux/mouse_cursor_monitor_pipewire.cc -new file mode 100644 -index 0000000..09dea24 ---- /dev/null -+++ b/third_party/libwebrtc/modules/desktop_capture/linux/mouse_cursor_monitor_pipewire.cc +diff -up firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/mouse_cursor_monitor_pipewire.cc.libwebrtc-screen-cast-sync firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/mouse_cursor_monitor_pipewire.cc +--- firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/mouse_cursor_monitor_pipewire.cc.libwebrtc-screen-cast-sync 2022-05-30 21:33:19.743522143 +0200 ++++ firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/mouse_cursor_monitor_pipewire.cc 2022-05-30 21:33:19.743522143 +0200 @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2022 The WebRTC project authors. All Rights Reserved. @@ -7647,11 +7577,9 @@ index 0000000..09dea24 +} + +} // namespace webrtc -diff --git a/third_party/libwebrtc/modules/desktop_capture/linux/mouse_cursor_monitor_pipewire.h b/third_party/libwebrtc/modules/desktop_capture/linux/mouse_cursor_monitor_pipewire.h -new file mode 100644 -index 0000000..9b9ccf7 ---- /dev/null -+++ b/third_party/libwebrtc/modules/desktop_capture/linux/mouse_cursor_monitor_pipewire.h +diff -up firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/mouse_cursor_monitor_pipewire.h.libwebrtc-screen-cast-sync firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/mouse_cursor_monitor_pipewire.h +--- firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/mouse_cursor_monitor_pipewire.h.libwebrtc-screen-cast-sync 2022-05-30 21:33:19.743522143 +0200 ++++ firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/mouse_cursor_monitor_pipewire.h 2022-05-30 21:33:19.743522143 +0200 @@ -0,0 +1,41 @@ +/* + * Copyright 2022 The WebRTC project authors. All Rights Reserved. @@ -7694,10 +7622,9 @@ index 0000000..9b9ccf7 +} // namespace webrtc + +#endif // MODULES_DESKTOP_CAPTURE_LINUX_MOUSE_CURSOR_MONITOR_PIPEWIRE_H_ -diff --git a/third_party/libwebrtc/modules/desktop_capture/linux/pipewire.sigs b/third_party/libwebrtc/modules/desktop_capture/linux/pipewire.sigs -index 3e21e9d..06a97b8 100644 ---- a/third_party/libwebrtc/modules/desktop_capture/linux/pipewire.sigs -+++ b/third_party/libwebrtc/modules/desktop_capture/linux/pipewire.sigs +diff -up firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/pipewire.sigs.libwebrtc-screen-cast-sync firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/pipewire.sigs +--- firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/pipewire.sigs.libwebrtc-screen-cast-sync 2022-05-27 01:17:03.000000000 +0200 ++++ firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/pipewire.sigs 2022-05-30 21:33:19.743522143 +0200 @@ -7,38 +7,44 @@ //------------------------------------------------ @@ -7757,21 +7684,18 @@ index 3e21e9d..06a97b8 100644 +pw_context *pw_context_new(pw_loop *main_loop, pw_properties *props, size_t user_data_size); +pw_core * pw_context_connect(pw_context *context, pw_properties *properties, size_t user_data_size); +pw_core * pw_context_connect_fd(pw_context *context, int fd, pw_properties *properties, size_t user_data_size); -diff --git a/third_party/libwebrtc/modules/desktop_capture/linux/pipewire_stub_header.fragment b/third_party/libwebrtc/modules/desktop_capture/linux/pipewire_stub_header.fragment -index 9d7dbd2..06ae18d 100644 ---- a/third_party/libwebrtc/modules/desktop_capture/linux/pipewire_stub_header.fragment -+++ b/third_party/libwebrtc/modules/desktop_capture/linux/pipewire_stub_header.fragment +diff -up firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/pipewire_stub_header.fragment.libwebrtc-screen-cast-sync firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/pipewire_stub_header.fragment +--- firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/pipewire_stub_header.fragment.libwebrtc-screen-cast-sync 2022-05-27 01:17:03.000000000 +0200 ++++ firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/pipewire_stub_header.fragment 2022-05-30 21:33:19.744522177 +0200 @@ -5,4 +5,5 @@ extern "C" { #include +#include } -diff --git a/third_party/libwebrtc/modules/desktop_capture/linux/scoped_glib.cc b/third_party/libwebrtc/modules/desktop_capture/linux/scoped_glib.cc -new file mode 100644 -index 0000000..51ca57a ---- /dev/null -+++ b/third_party/libwebrtc/modules/desktop_capture/linux/scoped_glib.cc +diff -up firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/scoped_glib.cc.libwebrtc-screen-cast-sync firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/scoped_glib.cc +--- firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/scoped_glib.cc.libwebrtc-screen-cast-sync 2022-05-30 21:33:19.744522177 +0200 ++++ firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/scoped_glib.cc 2022-05-30 21:33:19.744522177 +0200 @@ -0,0 +1,57 @@ +/* + * Copyright 2022 The WebRTC project authors. All Rights Reserved. @@ -7830,11 +7754,9 @@ index 0000000..51ca57a +} + +} // namespace webrtc -diff --git a/third_party/libwebrtc/modules/desktop_capture/linux/scoped_glib.h b/third_party/libwebrtc/modules/desktop_capture/linux/scoped_glib.h -new file mode 100644 -index 0000000..bf77855 ---- /dev/null -+++ b/third_party/libwebrtc/modules/desktop_capture/linux/scoped_glib.h +diff -up firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/scoped_glib.h.libwebrtc-screen-cast-sync firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/scoped_glib.h +--- firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/scoped_glib.h.libwebrtc-screen-cast-sync 2022-05-30 21:33:19.744522177 +0200 ++++ firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/scoped_glib.h 2022-05-30 21:33:19.744522177 +0200 @@ -0,0 +1,65 @@ +/* + * Copyright 2022 The WebRTC project authors. All Rights Reserved. @@ -7901,84 +7823,11 @@ index 0000000..bf77855 +} // namespace webrtc + +#endif // MODULES_DESKTOP_CAPTURE_LINUX_SCOPED_GLIB_H_ -diff --git a/third_party/libwebrtc/modules/desktop_capture/linux/screen_capturer_pipewire.cc b/third_party/libwebrtc/modules/desktop_capture/linux/screen_capturer_pipewire.cc -deleted file mode 100644 -index 3813d69..0000000 ---- a/third_party/libwebrtc/modules/desktop_capture/linux/screen_capturer_pipewire.cc -+++ /dev/null -@@ -1,28 +0,0 @@ --/* -- * Copyright 2018 The WebRTC project authors. All Rights Reserved. -- * -- * Use of this source code is governed by a BSD-style license -- * that can be found in the LICENSE file in the root of the source -- * tree. An additional intellectual property rights grant can be found -- * in the file PATENTS. All contributing project authors may -- * be found in the AUTHORS file in the root of the source tree. -- */ -- --#include "modules/desktop_capture/linux/screen_capturer_pipewire.h" -- --#include -- --namespace webrtc { -- --ScreenCapturerPipeWire::ScreenCapturerPipeWire() -- : BaseCapturerPipeWire(BaseCapturerPipeWire::CaptureSourceType::kScreen) {} --ScreenCapturerPipeWire::~ScreenCapturerPipeWire() {} -- --// static --std::unique_ptr --ScreenCapturerPipeWire::CreateRawScreenCapturer( -- const DesktopCaptureOptions& options) { -- return std::make_unique(); --} -- --} // namespace webrtc -diff --git a/third_party/libwebrtc/modules/desktop_capture/linux/screen_capturer_pipewire.h b/third_party/libwebrtc/modules/desktop_capture/linux/screen_capturer_pipewire.h -deleted file mode 100644 -index 66dcd68..0000000 ---- a/third_party/libwebrtc/modules/desktop_capture/linux/screen_capturer_pipewire.h -+++ /dev/null -@@ -1,33 +0,0 @@ --/* -- * Copyright 2018 The WebRTC project authors. All Rights Reserved. -- * -- * Use of this source code is governed by a BSD-style license -- * that can be found in the LICENSE file in the root of the source -- * tree. An additional intellectual property rights grant can be found -- * in the file PATENTS. All contributing project authors may -- * be found in the AUTHORS file in the root of the source tree. -- */ -- --#ifndef MODULES_DESKTOP_CAPTURE_LINUX_SCREEN_CAPTURER_PIPEWIRE_H_ --#define MODULES_DESKTOP_CAPTURE_LINUX_SCREEN_CAPTURER_PIPEWIRE_H_ -- --#include -- --#include "modules/desktop_capture/linux/base_capturer_pipewire.h" -- --namespace webrtc { -- --class ScreenCapturerPipeWire : public BaseCapturerPipeWire { -- public: -- ScreenCapturerPipeWire(); -- ~ScreenCapturerPipeWire() override; -- -- static std::unique_ptr CreateRawScreenCapturer( -- const DesktopCaptureOptions& options); -- -- RTC_DISALLOW_COPY_AND_ASSIGN(ScreenCapturerPipeWire); --}; -- --} // namespace webrtc -- --#endif // MODULES_DESKTOP_CAPTURE_LINUX_SCREEN_CAPTURER_PIPEWIRE_H_ -diff --git a/third_party/libwebrtc/modules/desktop_capture/linux/screencast_portal.cc b/third_party/libwebrtc/modules/desktop_capture/linux/screencast_portal.cc -new file mode 100644 -index 0000000..306e984 ---- /dev/null -+++ b/third_party/libwebrtc/modules/desktop_capture/linux/screencast_portal.cc +diff -up firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/screen_capturer_pipewire.cc.libwebrtc-screen-cast-sync firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/screen_capturer_pipewire.cc +diff -up firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/screen_capturer_pipewire.h.libwebrtc-screen-cast-sync firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/screen_capturer_pipewire.h +diff -up firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/screencast_portal.cc.libwebrtc-screen-cast-sync firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/screencast_portal.cc +--- firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/screencast_portal.cc.libwebrtc-screen-cast-sync 2022-05-30 21:33:19.744522177 +0200 ++++ firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/screencast_portal.cc 2022-05-30 21:33:19.744522177 +0200 @@ -0,0 +1,532 @@ +/* + * Copyright 2022 The WebRTC project authors. All Rights Reserved. @@ -8512,11 +8361,9 @@ index 0000000..306e984 +} + +} // namespace webrtc -diff --git a/third_party/libwebrtc/modules/desktop_capture/linux/screencast_portal.h b/third_party/libwebrtc/modules/desktop_capture/linux/screencast_portal.h -new file mode 100644 -index 0000000..7da218e ---- /dev/null -+++ b/third_party/libwebrtc/modules/desktop_capture/linux/screencast_portal.h +diff -up firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/screencast_portal.h.libwebrtc-screen-cast-sync firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/screencast_portal.h +--- firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/screencast_portal.h.libwebrtc-screen-cast-sync 2022-05-30 21:33:19.744522177 +0200 ++++ firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/screencast_portal.h 2022-05-30 21:33:19.744522177 +0200 @@ -0,0 +1,169 @@ +/* + * Copyright 2022 The WebRTC project authors. All Rights Reserved. @@ -8687,11 +8534,9 @@ index 0000000..7da218e +} // namespace webrtc + +#endif // MODULES_DESKTOP_CAPTURE_LINUX_SCREENCAST_PORTAL_H_ -diff --git a/third_party/libwebrtc/modules/desktop_capture/linux/shared_screencast_stream.cc b/third_party/libwebrtc/modules/desktop_capture/linux/shared_screencast_stream.cc -new file mode 100644 -index 0000000..c6ba661 ---- /dev/null -+++ b/third_party/libwebrtc/modules/desktop_capture/linux/shared_screencast_stream.cc +diff -up firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/shared_screencast_stream.cc.libwebrtc-screen-cast-sync firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/shared_screencast_stream.cc +--- firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/shared_screencast_stream.cc.libwebrtc-screen-cast-sync 2022-05-30 21:33:19.744522177 +0200 ++++ firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/shared_screencast_stream.cc 2022-05-30 21:33:19.744522177 +0200 @@ -0,0 +1,872 @@ +/* + * Copyright 2022 The WebRTC project authors. All Rights Reserved. @@ -9565,11 +9410,9 @@ index 0000000..c6ba661 +} + +} // namespace webrtc -diff --git a/third_party/libwebrtc/modules/desktop_capture/linux/shared_screencast_stream.h b/third_party/libwebrtc/modules/desktop_capture/linux/shared_screencast_stream.h -new file mode 100644 -index 0000000..72411e5 ---- /dev/null -+++ b/third_party/libwebrtc/modules/desktop_capture/linux/shared_screencast_stream.h +diff -up firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/shared_screencast_stream.h.libwebrtc-screen-cast-sync firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/shared_screencast_stream.h +--- firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/shared_screencast_stream.h.libwebrtc-screen-cast-sync 2022-05-30 21:33:19.744522177 +0200 ++++ firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/shared_screencast_stream.h 2022-05-30 21:33:19.744522177 +0200 @@ -0,0 +1,71 @@ +/* + * Copyright 2022 The WebRTC project authors. All Rights Reserved. @@ -9642,83 +9485,11 @@ index 0000000..72411e5 +} // namespace webrtc + +#endif // MODULES_DESKTOP_CAPTURE_LINUX_SHARED_SCREENCAST_STREAM_H_ -diff --git a/third_party/libwebrtc/modules/desktop_capture/linux/window_capturer_pipewire.cc b/third_party/libwebrtc/modules/desktop_capture/linux/window_capturer_pipewire.cc -deleted file mode 100644 -index c43a1f1..0000000 ---- a/third_party/libwebrtc/modules/desktop_capture/linux/window_capturer_pipewire.cc -+++ /dev/null -@@ -1,28 +0,0 @@ --/* -- * Copyright 2018 The WebRTC project authors. All Rights Reserved. -- * -- * Use of this source code is governed by a BSD-style license -- * that can be found in the LICENSE file in the root of the source -- * tree. An additional intellectual property rights grant can be found -- * in the file PATENTS. All contributing project authors may -- * be found in the AUTHORS file in the root of the source tree. -- */ -- --#include "modules/desktop_capture/linux/window_capturer_pipewire.h" -- --#include -- --namespace webrtc { -- --WindowCapturerPipeWire::WindowCapturerPipeWire() -- : BaseCapturerPipeWire(BaseCapturerPipeWire::CaptureSourceType::kWindow) {} --WindowCapturerPipeWire::~WindowCapturerPipeWire() {} -- --// static --std::unique_ptr --WindowCapturerPipeWire::CreateRawWindowCapturer( -- const DesktopCaptureOptions& options) { -- return std::make_unique(); --} -- --} // namespace webrtc -diff --git a/third_party/libwebrtc/modules/desktop_capture/linux/window_capturer_pipewire.h b/third_party/libwebrtc/modules/desktop_capture/linux/window_capturer_pipewire.h -deleted file mode 100644 -index 7f184ef..0000000 ---- a/third_party/libwebrtc/modules/desktop_capture/linux/window_capturer_pipewire.h -+++ /dev/null -@@ -1,33 +0,0 @@ --/* -- * Copyright 2018 The WebRTC project authors. All Rights Reserved. -- * -- * Use of this source code is governed by a BSD-style license -- * that can be found in the LICENSE file in the root of the source -- * tree. An additional intellectual property rights grant can be found -- * in the file PATENTS. All contributing project authors may -- * be found in the AUTHORS file in the root of the source tree. -- */ -- --#ifndef MODULES_DESKTOP_CAPTURE_LINUX_WINDOW_CAPTURER_PIPEWIRE_H_ --#define MODULES_DESKTOP_CAPTURE_LINUX_WINDOW_CAPTURER_PIPEWIRE_H_ -- --#include -- --#include "modules/desktop_capture/linux/base_capturer_pipewire.h" -- --namespace webrtc { -- --class WindowCapturerPipeWire : public BaseCapturerPipeWire { -- public: -- WindowCapturerPipeWire(); -- ~WindowCapturerPipeWire() override; -- -- static std::unique_ptr CreateRawWindowCapturer( -- const DesktopCaptureOptions& options); -- -- RTC_DISALLOW_COPY_AND_ASSIGN(WindowCapturerPipeWire); --}; -- --} // namespace webrtc -- --#endif // MODULES_DESKTOP_CAPTURE_LINUX_WINDOW_CAPTURER_PIPEWIRE_H_ -diff --git a/third_party/libwebrtc/modules/desktop_capture/mouse_cursor_monitor_linux.cc b/third_party/libwebrtc/modules/desktop_capture/mouse_cursor_monitor_linux.cc -index e569f6e..3bb51e8 100644 ---- a/third_party/libwebrtc/modules/desktop_capture/mouse_cursor_monitor_linux.cc -+++ b/third_party/libwebrtc/modules/desktop_capture/mouse_cursor_monitor_linux.cc +diff -up firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/window_capturer_pipewire.cc.libwebrtc-screen-cast-sync firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/window_capturer_pipewire.cc +diff -up firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/window_capturer_pipewire.h.libwebrtc-screen-cast-sync firefox-101.0/third_party/libwebrtc/modules/desktop_capture/linux/window_capturer_pipewire.h +diff -up firefox-101.0/third_party/libwebrtc/modules/desktop_capture/mouse_cursor_monitor_linux.cc.libwebrtc-screen-cast-sync firefox-101.0/third_party/libwebrtc/modules/desktop_capture/mouse_cursor_monitor_linux.cc +--- firefox-101.0/third_party/libwebrtc/modules/desktop_capture/mouse_cursor_monitor_linux.cc.libwebrtc-screen-cast-sync 2022-05-27 01:17:03.000000000 +0200 ++++ firefox-101.0/third_party/libwebrtc/modules/desktop_capture/mouse_cursor_monitor_linux.cc 2022-05-30 21:33:19.745522210 +0200 @@ -17,6 +17,10 @@ #include "modules/desktop_capture/linux/mouse_cursor_monitor_x11.h" #endif // defined(WEBRTC_USE_X11) @@ -9730,7 +9501,7 @@ index e569f6e..3bb51e8 100644 namespace webrtc { // static -@@ -44,6 +48,13 @@ MouseCursorMonitor* MouseCursorMonitor::CreateForScreen( +@@ -44,6 +48,13 @@ MouseCursorMonitor* MouseCursorMonitor:: // static std::unique_ptr MouseCursorMonitor::Create( const DesktopCaptureOptions& options) { @@ -9744,10 +9515,9 @@ index e569f6e..3bb51e8 100644 #if defined(WEBRTC_USE_X11) return MouseCursorMonitorX11::Create(options); #else -diff --git a/third_party/libwebrtc/modules/desktop_capture/screen_capturer_linux.cc b/third_party/libwebrtc/modules/desktop_capture/screen_capturer_linux.cc -index 57a2002..b44ae35 100644 ---- a/third_party/libwebrtc/modules/desktop_capture/screen_capturer_linux.cc -+++ b/third_party/libwebrtc/modules/desktop_capture/screen_capturer_linux.cc +diff -up firefox-101.0/third_party/libwebrtc/modules/desktop_capture/screen_capturer_linux.cc.libwebrtc-screen-cast-sync firefox-101.0/third_party/libwebrtc/modules/desktop_capture/screen_capturer_linux.cc +--- firefox-101.0/third_party/libwebrtc/modules/desktop_capture/screen_capturer_linux.cc.libwebrtc-screen-cast-sync 2022-05-27 01:17:03.000000000 +0200 ++++ firefox-101.0/third_party/libwebrtc/modules/desktop_capture/screen_capturer_linux.cc 2022-05-30 21:33:19.745522210 +0200 @@ -14,7 +14,7 @@ #include "modules/desktop_capture/desktop_capturer.h" @@ -9757,7 +9527,7 @@ index 57a2002..b44ae35 100644 #endif // defined(WEBRTC_USE_PIPEWIRE) #if defined(WEBRTC_USE_X11) -@@ -28,7 +28,7 @@ std::unique_ptr DesktopCapturer::CreateRawScreenCapturer( +@@ -28,7 +28,7 @@ std::unique_ptr Desktop const DesktopCaptureOptions& options) { #if defined(WEBRTC_USE_PIPEWIRE) if (options.allow_pipewire() && DesktopCapturer::IsRunningUnderWayland()) { @@ -9766,10 +9536,9 @@ index 57a2002..b44ae35 100644 } #endif // defined(WEBRTC_USE_PIPEWIRE) -diff --git a/third_party/libwebrtc/modules/desktop_capture/window_capturer_linux.cc b/third_party/libwebrtc/modules/desktop_capture/window_capturer_linux.cc -index ed03ba0..3bc6577 100644 ---- a/third_party/libwebrtc/modules/desktop_capture/window_capturer_linux.cc -+++ b/third_party/libwebrtc/modules/desktop_capture/window_capturer_linux.cc +diff -up firefox-101.0/third_party/libwebrtc/modules/desktop_capture/window_capturer_linux.cc.libwebrtc-screen-cast-sync firefox-101.0/third_party/libwebrtc/modules/desktop_capture/window_capturer_linux.cc +--- firefox-101.0/third_party/libwebrtc/modules/desktop_capture/window_capturer_linux.cc.libwebrtc-screen-cast-sync 2022-05-27 01:17:03.000000000 +0200 ++++ firefox-101.0/third_party/libwebrtc/modules/desktop_capture/window_capturer_linux.cc 2022-05-30 21:33:19.745522210 +0200 @@ -14,7 +14,7 @@ #include "modules/desktop_capture/desktop_capturer.h" @@ -9779,7 +9548,7 @@ index ed03ba0..3bc6577 100644 #endif // defined(WEBRTC_USE_PIPEWIRE) #if defined(WEBRTC_USE_X11) -@@ -28,7 +28,7 @@ std::unique_ptr DesktopCapturer::CreateRawWindowCapturer( +@@ -28,7 +28,7 @@ std::unique_ptr Desktop const DesktopCaptureOptions& options) { #if defined(WEBRTC_USE_PIPEWIRE) if (options.allow_pipewire() && DesktopCapturer::IsRunningUnderWayland()) { @@ -9788,11 +9557,10 @@ index ed03ba0..3bc6577 100644 } #endif // defined(WEBRTC_USE_PIPEWIRE) -diff --git a/third_party/moz.build b/third_party/moz.build -index 1941c11..f804531 100644 ---- a/third_party/moz.build -+++ b/third_party/moz.build -@@ -49,6 +49,12 @@ with Files("libwebrtc/**"): +diff -up firefox-101.0/third_party/moz.build.libwebrtc-screen-cast-sync firefox-101.0/third_party/moz.build +--- firefox-101.0/third_party/moz.build.libwebrtc-screen-cast-sync 2022-05-27 01:17:04.000000000 +0200 ++++ firefox-101.0/third_party/moz.build 2022-05-30 21:33:19.745522210 +0200 +@@ -58,6 +58,12 @@ with Files("libwebrtc/**"): with Files("pipewire/**"): BUG_COMPONENT = ("Core", "WebRTC") @@ -9805,11 +9573,10 @@ index 1941c11..f804531 100644 with Files('rlbox_wasm2c_sandbox/**'): BUG_COMPONENT = ('Firefox Build System', 'General') -diff --git a/third_party/pipewire/libpipewire/mozpipewire.cpp b/third_party/pipewire/libpipewire/mozpipewire.cpp -index 1ecfc31..fbeeb8e 100644 ---- a/third_party/pipewire/libpipewire/mozpipewire.cpp -+++ b/third_party/pipewire/libpipewire/mozpipewire.cpp -@@ -69,11 +69,13 @@ static int (*pw_stream_connect_fn)(struct pw_stream *stream, +diff -up firefox-101.0/third_party/pipewire/libpipewire/mozpipewire.cpp.libwebrtc-screen-cast-sync firefox-101.0/third_party/pipewire/libpipewire/mozpipewire.cpp +--- firefox-101.0/third_party/pipewire/libpipewire/mozpipewire.cpp.libwebrtc-screen-cast-sync 2022-05-27 01:17:03.000000000 +0200 ++++ firefox-101.0/third_party/pipewire/libpipewire/mozpipewire.cpp 2022-05-30 21:33:19.745522210 +0200 +@@ -69,11 +69,13 @@ static int (*pw_stream_connect_fn)(struc enum pw_stream_flags flags, const struct spa_pod **params, uint32_t n_params); @@ -9823,7 +9590,7 @@ index 1ecfc31..fbeeb8e 100644 static int (*pw_stream_queue_buffer_fn)(struct pw_stream *stream, struct pw_buffer *buffer); static int (*pw_stream_update_params_fn)(struct pw_stream *stream, -@@ -87,7 +89,10 @@ static int (*pw_thread_loop_start_fn)(struct pw_thread_loop *loop); +@@ -87,7 +89,10 @@ static int (*pw_thread_loop_start_fn)(st static void (*pw_thread_loop_stop_fn)(struct pw_thread_loop *loop); static void (*pw_thread_loop_lock_fn)(struct pw_thread_loop *loop); static void (*pw_thread_loop_unlock_fn)(struct pw_thread_loop *loop); @@ -9873,7 +9640,7 @@ index 1ecfc31..fbeeb8e 100644 } return IsPwLibraryLoaded(); -@@ -242,6 +255,15 @@ pw_stream_connect(struct pw_stream *stream, +@@ -242,6 +255,15 @@ pw_stream_connect(struct pw_stream *stre params, n_params); } @@ -9889,7 +9656,7 @@ index 1ecfc31..fbeeb8e 100644 struct pw_buffer * pw_stream_dequeue_buffer(struct pw_stream *stream) { -@@ -356,6 +378,23 @@ pw_thread_loop_unlock(struct pw_thread_loop *loop) +@@ -356,6 +378,23 @@ pw_thread_loop_unlock(struct pw_thread_l return pw_thread_loop_unlock_fn(loop); } @@ -9913,7 +9680,7 @@ index 1ecfc31..fbeeb8e 100644 struct pw_properties * pw_properties_new_string(const char *str) -@@ -366,3 +405,12 @@ pw_properties_new_string(const char *str) +@@ -366,3 +405,12 @@ pw_properties_new_string(const char *str return pw_properties_new_string_fn(str); } diff --git a/mozilla-1663844.patch b/mozilla-1663844.patch index 6c2392f..d356425 100644 --- a/mozilla-1663844.patch +++ b/mozilla-1663844.patch @@ -1,6 +1,6 @@ -diff -up firefox-84.0/dom/media/gmp/GMPSharedMemManager.h.1663844 firefox-84.0/dom/media/gmp/GMPSharedMemManager.h ---- firefox-84.0/dom/media/gmp/GMPSharedMemManager.h.1663844 2020-12-07 23:32:59.000000000 +0100 -+++ firefox-84.0/dom/media/gmp/GMPSharedMemManager.h 2020-12-10 12:59:39.287832851 +0100 +diff -up firefox-101.0/dom/media/gmp/GMPSharedMemManager.h.1663844 firefox-101.0/dom/media/gmp/GMPSharedMemManager.h +--- firefox-101.0/dom/media/gmp/GMPSharedMemManager.h.1663844 2022-05-27 01:16:53.000000000 +0200 ++++ firefox-101.0/dom/media/gmp/GMPSharedMemManager.h 2022-05-30 21:15:20.989993419 +0200 @@ -27,7 +27,7 @@ class GMPSharedMem { // returned to the parent pool (which is not included). If more than // this are needed, we presume the client has either crashed or hung @@ -10,22 +10,21 @@ diff -up firefox-84.0/dom/media/gmp/GMPSharedMemManager.h.1663844 firefox-84.0/d GMPSharedMem() { for (size_t i = 0; i < sizeof(mGmpAllocated) / sizeof(mGmpAllocated[0]); -diff -up firefox-84.0/dom/media/platforms/agnostic/gmp/GMPDecoderModule.cpp.1663844 firefox-84.0/dom/media/platforms/agnostic/gmp/GMPDecoderModule.cpp ---- firefox-84.0/dom/media/platforms/agnostic/gmp/GMPDecoderModule.cpp.1663844 2020-12-10 12:59:39.287832851 +0100 -+++ firefox-84.0/dom/media/platforms/agnostic/gmp/GMPDecoderModule.cpp 2020-12-10 14:05:00.833685947 +0100 -@@ -82,7 +82,7 @@ bool GMPDecoderModule::SupportsMimeType( +diff -up firefox-101.0/dom/media/platforms/agnostic/gmp/GMPDecoderModule.cpp.1663844 firefox-101.0/dom/media/platforms/agnostic/gmp/GMPDecoderModule.cpp +--- firefox-101.0/dom/media/platforms/agnostic/gmp/GMPDecoderModule.cpp.1663844 2022-05-30 21:15:20.989993419 +0200 ++++ firefox-101.0/dom/media/platforms/agnostic/gmp/GMPDecoderModule.cpp 2022-05-30 21:24:16.615282035 +0200 +@@ -66,6 +66,7 @@ media::DecodeSupportSet GMPDecoderModule - bool GMPDecoderModule::SupportsMimeType( - const nsACString& aMimeType, DecoderDoctorDiagnostics* aDiagnostics) const { -- return false; -+ return MP4Decoder::IsH264(aMimeType); - } + nsCString api = nsLiteralCString(CHROMIUM_CDM_API); - /* static */ -diff -up firefox-84.0/dom/media/platforms/agnostic/gmp/GMPVideoDecoder.cpp.1663844 firefox-84.0/dom/media/platforms/agnostic/gmp/GMPVideoDecoder.cpp ---- firefox-84.0/dom/media/platforms/agnostic/gmp/GMPVideoDecoder.cpp.1663844 2020-12-08 00:35:04.000000000 +0100 -+++ firefox-84.0/dom/media/platforms/agnostic/gmp/GMPVideoDecoder.cpp 2020-12-10 12:59:39.287832851 +0100 -@@ -67,6 +67,8 @@ void GMPVideoDecoder::Decoded(GMPVideoi4 ++ // TODO: Do we enable it here? + if (MP4Decoder::IsH264(aMimeType)) { + isSupported = HaveGMPFor(api, {"h264"_ns, aGMP.value()}); + } else if (VPXDecoder::IsVP9(aMimeType)) { +diff -up firefox-101.0/dom/media/platforms/agnostic/gmp/GMPVideoDecoder.cpp.1663844 firefox-101.0/dom/media/platforms/agnostic/gmp/GMPVideoDecoder.cpp +--- firefox-101.0/dom/media/platforms/agnostic/gmp/GMPVideoDecoder.cpp.1663844 2022-05-27 01:16:53.000000000 +0200 ++++ firefox-101.0/dom/media/platforms/agnostic/gmp/GMPVideoDecoder.cpp 2022-05-30 21:15:20.989993419 +0200 +@@ -70,6 +70,8 @@ void GMPVideoDecoder::Decoded(GMPVideoi4 RefPtr self = this; if (v) { mDecodedData.AppendElement(std::move(v)); diff --git a/sources b/sources index 381f526..39a05eb 100644 --- a/sources +++ b/sources @@ -1,4 +1,4 @@ SHA512 (cbindgen-vendor.tar.xz) = b9ab1498be90ecf60822df7021f8812f124550d97f8cd687c69d3ab56fc5fb714bfe88c78c978a1794d211724909a9a5cad6a4b483fa05f762909c45d5075520 SHA512 (mochitest-python.tar.gz) = 18e1aeb475df5fbf1fe3838897d5ac2f3114aa349030713fc2be27af087b1b12f57642621b87bd052f324a7cb7fbae5f36b21502191d85692f62c8cdd69c8bf2 -SHA512 (firefox-100.0.2.source.tar.xz) = 6d9922e35e496fa63833ba03d1466e075287e40e50854ddc4f4a2036d9c7ca1f35c03bc6f708a3c469e0ec3b389b3346ac754bb84df0fecb86955fc21c05e00f -SHA512 (firefox-langpacks-100.0.2-20220520.tar.xz) = 12ce91a452cef7937c6b25623a00fa2d2aedea3b7856bbbd3c0ee2cf08f55d525aa5e2b91d11e265b58f4b4505930d99b7a5d295d9cd92839ada3e3850e181af +SHA512 (firefox-101.0.source.tar.xz) = fffe7e0940c1443fcdc5b205677764cb4e04b29f33fcfafb2857d383700584f309806b81fc4989efb56cc12a3cca1ff7d451b647050c43e98777b5c952ed5d56 +SHA512 (firefox-langpacks-101.0-20220530.tar.xz) = aa81113b6aef965aa17921d563759da6c499021b6f471369d998c35802f72e79a107080b4df59ca51dae15ac464176f23bce2fc84942f5852e810d963553b687 -- cgit